Help on simulating a ms2s transition with HFSS

Just a thought about your 45 microns slot.
Etching will not give a vertical wall, but a somewhat trapezoidal cross-section and when the height is 17 microns it makes a difference. And that does not include the error due to the imprecision with which those 45 microns can be achieved (at the top, bottom or middle ? your choice).
The best thing is to ask some manufacturers about those issues, since they know exactly their limits and tolerances.
In my opinion your design is very sensitive to that width since the field is the most intense there (at least for some frequencies) ? so the manufacturing errors and tolerances I mentioned can change the results significantly.

Thanx fekete,

come on friends I really need this simulation results with hfss, I don't know how much time it takes in hfss, but in the software I used it takes only 25 minutes.

aze

I?ve run a MWS simulation, however I didn?t have too much time and I had to stop the simulation after 2 adaptive mesh passes, and it wasn?t converged yet.
Yes, it takes longer times to simulate with a 3D solver, especially because you have such small features ? better to use a 2.5D solver for planar problems.
Did you consider the conductivity of the metal? If yes did you discretize the volume of the metal (like with EM3DS)?
I did that with MWS, and that also increases the computation time.
See the S parameters after the second pass attached.

I tried to send you a message but it has stopped in the Outbox folder and never went to Sent (don?t know why) So I?ll post it here.

Hi aze,

You should ask manufacturers of pcbs. You should mention that only one line is so small and the design is very simple.
See for example
http://www.custompcb.com/
http://www.dialelectrical.co.uk/product-4787266.html

An example of company that offers a 100 micron width minimum, but the resolution is 6 microns - which is significant.
http://www.delorenzo.com.mx/esp/prod...ick_circ_5.htm


This next one has 50 micron trace limit, but 75 microns slot width:
http://www.cirexx.com/ps/fabrication.html


Kyocera offers 25 microns width limit but it is very expensive:
http://www.kyocera-slc.co.jp/english...cts/index.html

regards,
f

Hi All,

thanx fekete for your help,

I upload a rar file containing the simulation results for the circuit above, and I would like to ask if these results are goud enough to start making a prototype.

aze.

Hi aze,

Your results look more like the results I?ve got with MWS after the first pass (see attached S param). I wonder if you did a dense enough meshing with your simulator.
Note that the minimum(s) on S11 moved to lower frequency for pass2 - ie better mesh.
The MWS pass2 results look better than yours, a flatter S21 ? what are your target/desired parameters?

Another issue is the manufacturing tolerances, try simulating your structure with a 40 microns and once with a 50 microns width slot (assuming a 5 microns tolerance). See if the differences in results are significant.

What company is making the board?

f

Hi fekete,

thanx for your time I apreciate;

* my targets are:

- a band as wide as possible around 12 GHz for ex : 6 to 18 GHz will be great.

- S11 (simulation) < -15 dB.

- S21(simulation) > -1dB .

- vswr < 1.5.

* about your advice to simulate with different slot width:

- when I simulate with w<45 microns it will generate an error I think because of slot width over lambda_0 must exceed 0.0015 according to Gupta's book.

- when I simulate with w> 45 microns the results are less good. ie the band get narrower I tryed with 100 microns.



* another question what taper shape do you advise me to use for the TSA?

Thanx again.

aze.

hi, anyone tried simulating a microstrip to slotline transition when port 1 at microstrip 50ohm and port 2 at slotline? I keep on having problem with the port impedance and the port size.

When i follow the 4h x 7g port size , there is always a cutoff which the port size cant support. I am trying to simulate from 1GHz to 18Ghz. Thanks