About EMI solution at chip layout stage and board/system

Hi,

Could you please tell me how to reduce noise and/or EMI in the chip layout stage? And how to reduce noise from SOC device to board/system? What are the related EDA tools?

Thanks a lot.

Best Regards,
risccpu

There are numerous ways. Some things off the top of my head:
Guard rings.
Separate bond-outs for high current, low noise, or switching sections to minimize ground bounce.
Careful routing to minimize ground loops.
Appropriate use of bypass capacitors.
Fully differential topologies
Careful selection of the clock frequencies

http://web.awrcorp.com/Usa/Products/Signal%2DIntegrity/
http://www.ansoft.com/products/si/siwave/
http://www.mentor.com/products/pcb/a...ion/hyperlynx/

There's an article on signal integrity at wikipedia .

Agilent EEsof EDA makes EDA tools for multigigabit per second signal integrity analysis

hth