which tool can i use to simulate and design the PGS inductor on si chip?
I'm a new guy for designing the ic.Now i want to design a PGS(Patterned Ground Shields) inductor on si chip. can i use the ASITIC to design PGS and get the parasitic parament .where can i get the TMSC18.dek FILE.
thank you for your concern.
Asitic is not very accurate, but it is nice to get a starting point ("quick & dirty"). You could manually create a ground shield by adding many ground wires.
For most technologies, the stackup is considered confidential and only shared under an NDA. After signing the NDA, you will get some process documentation which includes the stackup information, so that you can create the Asitic tech file.
If you want an accurate result, use Sonnet. This is also more accurate for RFIC work than the so called "full 3D solvers", and it is much better integrated into the Cadence design flow.
For Sonnet, you can import the stackup from the Assura procfile that comes with the Cadence design kit. If you want to create it manually, there is a stackup editor for Sonnet to visualize and edit the stackup as needed. http://muehlhaus.com/products/material-file-utility