EMI reduction with spread spectrum modulated clock. Help to choose right IC.
I need SS clock for FPGA while ADC should be clocked from reference clock (clock without SS, that I plan to use as reference of SS IC).
So I need modulated clock in phase with the reference one. (Of cause I extend input constrain for FPGA, it is possible).
The feature required for me is called "timing-safe" in ON Semi documentation.
See app.note:
www.onsemi.com/pub_link/Collateral/AND8443-D.PDF
The "conventional SSC" - figure 5 on page 3 is not suitable. Because the clock edge is spreaded across the whole period.
I checked P2781AF IC and it behavior is "conventional SSC".
But the ICs with "timing-safe" feature are not available. There are no such IC in stock and lead time and/or minimal amount very big.
P3P623S00BG
P3PSL450AHG
P3P85R01A
So is there similar IC from other vendors? What is the other vendors "marketing" name of similar feature?
TNX!
Sergey.
Perhaps what you really want is a pair of variable delay
line (VCD) elements, decently matched; one at fixed
and centered delay for the main clock, and one variable.
You could select the delay min/max to be whatever
portion of the period you like. You could also put the
"center reference" delay in the PLL feedback path if
you need to remain synchronous with some upstream
clock, and take the spread-clock off the same input
point so it spreads about zero (if this is indeed what
you want - you might like a one-sided delay for some
timing reason).
Now there's spectrum spreading as a means of fooling
a standard test method, and there's the rest. The
test-method foolery may get you past a check-box
without really helping circuit response issues that
revolve around single edge timing placement or
impulse noise from the edges; it's only baseband and
harmonic amplitude as displayed by a slow specAn
that is helped.
Yes, my purpose is to pass EMI test. I do understand, that it is some fooling due to integration time of EMI tester, but it is required.
I do not have an expirience with EMI tests, so first I wish to check some "generic" solution, and then I'll try to redesign my PCB.
I need a low cost, suitable for mass production solution. It should be small size and do not consume CPU performance or FPGA resources.
Your suggestion with two delay lines is clean, but to implement it I need find delay line IC with controlled delay, or to design something with RC and free FPGA pins - it is not suitable for my purpose. In addition it is required some expiriements with modulation of the delay, I am not sure that saw wave on delay line control will be good enough to fooling EMI test.
In other words the suggested approach is too complex.
---------
Let me add my "theoretical" opinion: the design of SS modulator very similar to "fractional" PLL. So It can be viewed as PLL with controled delay in feedback. But I did not understand, why the clock edge of SSC is blurred on whole period of reference clock instead of some "jitter" around reference clock edge.
Why put all your effort into cheating ?
Why not fix the damned thing so it does not radiate in the first place ?
If you would be OK with doing this within the FPGA (?)
then I might suggest a linear feedback shift register
(PRNG) that uses bits to add or bypass gate delay
stages. Let each clock edge change slightly the next.
Using PRNG-driven switches to connect small capacitors
(if you can get to that level of routing "touch") is another
and perhaps finer-grained option.
In my opinion, SSC is a standard EMI reduction method. At least several major IC producers (TI, IDT, Cypress, ON Semi, Actel ...) make IC for this.
Using spectrum analyzer I found that main radiation source is RF shield. I do not have an idea what I should correct in the pcb yet. And the most important thing: to produce new pcb revision one need month or more time, while SSC IC on breadboard can be inserted instead of clock driver series resistor in several minutes.
But if I'll not find SSC solution - I'll start pcb redesign (now I do HL simulation and trying to involve RF engineer into the issue).
I wish to implement it on present board. I am not ready to investigate SSC modulation.
Due to the thread I understand that SSC EMI reduction IC is not so common. Probably I should either reject this idea or purchase "timing-safe" ON Semi IC and try it.