PEX-output-netlist-use names from option
时间：03-25
整理：3721RD
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Hi everyone
I have some problem with using "PEX-output-netlist-use names from" option. I am using TSMC 65nm PDK. According to the PDK doc, I am supposed to choose PEX-output-netlist-use names from option to be "source based" instead of other options including "schematic/layout/schematiconly".
But there are some errors. I list them at the end of this post.
Trying to fix the error, I use "schematic", the simulation result is correct. the PEX also separate each finger of the transistors but no finger is missing. But when I decided to use schematic based for later simulation, I read this from Calibre doc
"
The ?SOURCE-BASED? and ?SCHEMATIC ONLY? options are most appropriate
for Calibre View creation and other back-annotation flows, since the parasitic netlist
is based on the source schematic."
Can anyone let me know what should I do?
Thanks
Allen
error description:
1. PEX can only extract 1 finger per transistor(so the DC level are way off compared to the schematic level simulation due to the w of a MOSFET become 1/number of fingers). So I have to manually change the number of fingers in the calibre view to the right finger number. This solution works for most of the cases.
2. I designed a flipflop with 6 identical NAND gates. If I only extract each NAND gate and connect them in the schematic, the circuit is working. But only 1 of my NAND gates could not work when I connect it into a flipflop in the LAYOUT, then PEX and simulate. That specific NAND gate give me a Vlow ~=vhigh. The DRC and LVS are all Passed. I tried just extract R but the error persists. and I change each of the parasitic R value to 0.0001Ohm, the error is still there. I assume the error is due to the name of the terminals because when I choose "PEX-output-netlist-use names from-schematic", the PEX works fine.
I have some problem with using "PEX-output-netlist-use names from" option. I am using TSMC 65nm PDK. According to the PDK doc, I am supposed to choose PEX-output-netlist-use names from option to be "source based" instead of other options including "schematic/layout/schematiconly".
But there are some errors. I list them at the end of this post.
Trying to fix the error, I use "schematic", the simulation result is correct. the PEX also separate each finger of the transistors but no finger is missing. But when I decided to use schematic based for later simulation, I read this from Calibre doc
"
The ?SOURCE-BASED? and ?SCHEMATIC ONLY? options are most appropriate
for Calibre View creation and other back-annotation flows, since the parasitic netlist
is based on the source schematic."
Can anyone let me know what should I do?
Thanks
Allen
error description:
1. PEX can only extract 1 finger per transistor(so the DC level are way off compared to the schematic level simulation due to the w of a MOSFET become 1/number of fingers). So I have to manually change the number of fingers in the calibre view to the right finger number. This solution works for most of the cases.
2. I designed a flipflop with 6 identical NAND gates. If I only extract each NAND gate and connect them in the schematic, the circuit is working. But only 1 of my NAND gates could not work when I connect it into a flipflop in the LAYOUT, then PEX and simulate. That specific NAND gate give me a Vlow ~=vhigh. The DRC and LVS are all Passed. I tried just extract R but the error persists. and I change each of the parasitic R value to 0.0001Ohm, the error is still there. I assume the error is due to the name of the terminals because when I choose "PEX-output-netlist-use names from-schematic", the PEX works fine.