microstrip vias de-embedding

Hi, Wlcsp: What do you mean "de-embed the vias in microstrip lines"? Please explain a little bit detail on what you want to achieve. Regards.

Microstrip consists of signal line and ground plane.
However, if we want to measure using GSG probes, we need to connect the ground pad to ground plane through vias. My question is: how to de-embed the effect of the via.

thanks,
wlcsp

Hi, Wlcsp: I understand what you want to achieve now. Basically, the measurement has a setup for GSG measurement in the physical layout. You got the s-parameters including the GSG while you want to exclude its effect.

I am not sure how you can calibrate it in measurement. However, in simulation, we can achieve what you want. Ideally, we don't want to simulate GSG because feeding the microstirp directly is much simpler in simulation (I will refer the case as M). However, we can still simulate it as GSG. In MODUA of IE3D package, we have some features called "BACK SIMULAITON", "SEPARATE S-PARAMETERS" and "REMOVE S-PARAMETERS". They allow you to perform algebraic like operations on s-parameters. For example, you simulate and get the M case's 2-port s-parameters as SpM. You simulate and get the GSG case's 2-port s-parameters as SpGSG. Basically, you can consider the SpGSG as the cascading of SpM and some SpConnector. On IE3D, you can simulate the SpM and the SpGSG. Therefore, you can use the features on MODUA to dervie SpConnector from SpGSG and SpM. Symbolically, you can consider SpGSG = SpConnector1 + SpM + SpConnector2 and we are able to sovle the SpConnector from this algebraic equations on MODUA. It is a sophisticated process even though it is simple in this algebraic like formula. Regards.

Jian, thanks a lot for the explanation.
I don't think combining simulation and measurement is a good idea.
Let me describe my problem in more specific way:
I have a microstrip structure (to be fabricated) that consists of signal line, ground plane, contact pads for the probes, and vias. By applying open de-embedding structure, one can get rid of the effect of pad capacitances. Now, what we have is:
[A_left_via]*[A_microstrip]*[A_right_via]=[A_measured]; where A denotes the abcd matrix. The only information we have are [A_measured] and [A_thru]=[A_left_via]*[A_right_via].

Open-short de-embedding cannot be implemented as in the case of CPW.
Do you have any suggestion or references to this matter?

thanks,
wlcsp

Hi, wlcsp:

The way I described in MODUA of IE3D accessory is not only for simulations. It is also good for any s-parameters including measured data. However, I understand that you may not be able to find the s-parameters without connectors because they are what you are after.

From what I see, if your A_left_via and A_right_via is completely symmetrical and identical, you should be able to find A_left_via from A_thru. After you find A_left_via (and A_right_via), you should be able to find A_microstrip from A_measured and A_left_via. The 2nd procedure is implemented into MODUA. For the 1st one, I had some something on it. However, it is not in our released software. We can consider releasing it on MODUA. Regards.

You usually build some TRL or LRM calibration starndards into your die or thin-flim. Or else make a seperate one on the same process. This way you can de-embed out the CPW to microstrip transistion.

There is also an assumption implicit in this line of thinking that you have already calibrated your measurement probe so that your measurement reference plane is at the probe tips. Don't forget that this is best done using the same exact substrate that you are measuring your part on.

madengr has the best advice; build TRL or LRM (or whatever cal method you feel is best for your application) calibration standards on the same wafer or fab run that you are using. And don't forget to include a couple of simple through lines to test the quality of your calibration.

--Max

Jian, A_left_via and A_right_via are not symmetrical. However, I will consider your first idea. It seems promising. The problem is, i don't have IE3D :(

wlcsp

Hi, wlcsp:

There are two conditions there:

1. A_left and A_right are symmetrical
2. A_left and A_right are identical.

If any of the 2 conditions is not met, you will not have a unique solution mathematically. From the A_measured and A_thru, you will not be able to find the A_left and A_right and A_microstrip.

You mentioned the 1st scheme. Do you mean the scheme using EM simulation results? Free IE3D evaluation license is available on the web (www.zeland.com). Thanks!

Yes, using the tool from IE3D. I will also go for TRL de-embedding. I actually don't like to build my own calibration structure on the wafer, since we don't know the exact properties of the silicon wafer (resistivity 2-5 ohm-cm).
Concerning the via structure:
A_left=[a b;c d] A_right=[d b;c a] This makes the thru structure
A_thru=A_left*A_right

Another plan I am going for is: build a via-less CPW-to-microstrip transition structure. Thus, microstrip characteristic will be obtained. From this, I can always characterize the via if I want to.

thanks,
wlcsp

I tried the TRL in the simulation. I works very well. I will have them on the wafer. Thanks a lot guys.