ignore inductance

Hi All,

Could you tell me under what condition I can ignore the inductance for interconnect in terms of timing and/or coupling noise? Is there some kind of formula or rule of thumb?

Thanks.

It depends on the speed of your signals, or more importantly, the rise time, going across the interconnect. If they are high speed signals, since inductance increases with frequency, higher frequency signals will have greater inductance, causing greater impedance, causing more crosstalk and noise etc... if you are doing low-speed stuff, you can ignore it.

Thanks, jdhar. Do you know any formula which I can use to evaluate the on-chip interconnect for inductance?

On-chip? I'm not sure about this, you can search for Johnson's book on High-speed digital design, but that deals more with board-level stuff. I have a feeling you may need an EM simulator if you are doing on-chip stuff.