用hspice进行PLL testbench面临的问题
时间：10-02
整理：3721RD
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我希望能够看到PLL在已知ref clk 锁定的情况下，增加相位阶跃，频率阶跃，以及频率斜坡三种情况下的PLL锁定时间和锁定范围，请问，应该怎么加这种信号源呢?
用phase domain或者frequency domain的线性模型做。
LS上具体些吗?
If the same signal were tested with a shorter ruler, say, 0.25 unit intervals long, then the ruler would certainly be crossed less frequently. Perhaps only one waveform out of every 100,000
waveforms, on average, would cross this shorter ruler. One could say that, aside from one waveform in 10 , the eye was 25% open.
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