SNDR in Current Steering DAC
时间：10-02
整理：3721RD
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Hi all ,
Resently I have simulated the SNDR of a 12b Current sterring DAC ,but it is only 54dB, thus the enob is 9bit . Simulation by Cadence without mc model.
So, I'm very confused why the DAC's SNDR was so bad ?
Can anyone give me some help?
By the way, How to tradoff the transistors' size of current source for the Statics and Dynamic performance ?
Best regards！
lvbq
Resently I have simulated the SNDR of a 12b Current sterring DAC ,but it is only 54dB, thus the enob is 9bit . Simulation by Cadence without mc model.
So, I'm very confused why the DAC's SNDR was so bad ?
Can anyone give me some help?
By the way, How to tradoff the transistors' size of current source for the Statics and Dynamic performance ?
Best regards！
lvbq
At first you should provide some circuit structure information and simulation results, so we can analysis the issue.
How about the DNL/INL character of your DAC?
没用校准的话，输出阻抗继续加大吧，没别的
电流管L做大点，开关管面积小点，静态的靠DEM，动态的靠开关交越点调整或者dummy开关什么的
OK，Thanks
OK，Thanks