数字综合 异步时钟

求助：
您好，各位，小弟最近在综合一个代码，功能是将输入时钟fi与参考时钟fr比较，若fi/fr=109,就输出lock_o=1并输出输出相应的数据，否则lock_o=0，fi与fr是不同源的两个时钟，综合的时候出现错误了（如下）。
Warning！Timing violation
$setuphold<hold>( posedge CK &&& (flag == 1):999998567 NS, negedge D:999998567 NS,1.000 : 1 NS,0.500 : 500 PS );
File: /data3/library/umc18_artisan_fb/aci/sc-x/verilog/umc18.v, line = 8145
Scope: tb_SD_PART.s1.\count_tmp_reg[2]
Time: 999998567 NS
请问如何修改呀?谢谢！
源代码：
`timescale 1ns / 1ns
module SD_PART(rst, fr, fi, qout_o, wr, lock_o);
inputrst;
inputfr;
inputfi;
output [6:0] qout_o;
outputwr;
outputlock_o;
reglock_o;
regfr_tmp;
reg [7:0] count;
reg [7:0] count_tmp;
wiren_fr_tmp;
wire [8:0] tmp;
wire [9:0] tmp_lock;
reg [8:0] sum;
reg [8:0] sum1;
reg [8:0] sum2;
reg [8:0] sum3;
reg [8:0] p_tmp;
// fr divide by 2
always @(posedge fr or negedge rst)
begin
if(！rst) fr_tmp <= #1 1'b0;
elsefr_tmp <= #1 ~fr_tmp;
end
assign n_fr_tmp = ~fr_tmp;
// counter for fr_tmp
always @(posedge fi or negedge fr_tmp)
begin
if(！fr_tmp) count <= #1 8'h0;
elsecount <= #1 (count==8'hff) ? 8'hff : count + 1'b1;
end
// Q out signal generate
always @(posedge n_fr_tmp or negedge rst)
begin
if(！rst) count_tmp <= #1 8'h0;
elsecount_tmp <= #1 count;
end
assign tmp = 8'd109 - count_tmp;
always @(posedge n_fr_tmp or negedge rst)
begin
if(！rst) sum <= #1 9'h0;
elsesum <= #1 tmp + sum;
end
assign qout_o = sum[8:2];
assign wr = fr_tmp;
// lock signal generate
always @(posedge n_fr_tmp or negedge rst)
begin
if(！rst)
begin
sum1 <= #1 9'h0;
sum2 <= #1 9'h0;
sum3 <= #1 9'h0;
end
else
begin
sum1 <= #1 sum;
sum2 <= #1 sum1;
sum3 <= #1 sum2;
end
end
assign tmp_lock = sum3 - sum;
always @(tmp_lock)
begin
if(tmp_lock[9]) p_tmp = ~tmp_lock[8:0] + 1'b1;
elsep_tmp = tmp_lock[9:0];
end
always @(posedge n_fr_tmp or negedge rst)
begin
if(~rst) lock_o <= #1 1'b0;
elselock_o <= #1 (p_tmp<9'h3) ? 1'b1 : 1'b0;
end
endmodule

这个你应该发到数字板块