TLV320AIC3106阻抗匹配

你好，我正在进行叠构设计，我想了解一下tlv320aic3106有无特殊信号需要阻抗匹配的？如果没有，那么一般的单端信号的阻抗范围又是多少呢？望指教，谢谢。

你好：

可否解释一下叠构设计是什么意思？很抱歉，我不太明白你在使用AIC3106的过程中，顾虑是什么？

阻抗范围，可以参照datasheet page 8的表格中，有一个 input resisitance， 可以看一下这个是不是你需要的。

hi flora :

thx!

叠构就是strack-up，也就是多层PCB的叠层构造，最主要考虑的是信号线，而这次我所担心的是噪声问题。具体的你可以在网上搜寻相关资料。

另问题已经解决，现贴于此作为大家的参考学习吧。

Hello,

Impedance matching from a source to the input impedance of the part is not necessary.  Likewise, matching the output impedance of the part to an external load is not necessary. This is not a good idea since it will cause large voltage division.

Generally, your sources should be low impedance relative to the input impedance. The load impedance should be large relative to the output impedance.

For differential inputs, it is always recommended to match the impedance of the + and  - input pair. DC blocking capacitors on these inputs should be X5R or better with tight tolerances to ensure that the impedance is the same. The trace length and routing should also be as identical as possible to keep stray inductance and capacitances equally distributed.

Regards,

Matt