有关uvm验证的问题

1. `timescale 1ns/1ps
   
2. `include "uvm_pkg.sv"
   
3. 
   
4. 
   
5. module top_tb;
   
6. import uvm_pkg::*;
   
7. `include "uvm_macros.svh"
   
8. 
   
9. reg clk;
   
10. reg rst_n;
    
11. reg[7:0] rxd;
    
12. reg rx_dv;
    
13. wire[7:0] txd;
    
14. wire tx_en;
    
15. 
    
16. class my_driver extends uvm_driver;
    
17. 
    
18. function new(string name = "my_driver", uvm_component parent = null);
    
19. super.new(name, parent);
    
20. endfunction
    
21. extern virtual task main_phase(uvm_phase phase);
    
22. 
    
23. endclass
    
24. 
    
25. task my_driver::main_phase(uvm_phase phase);
    
26. top_tb.rxd <= 8'b0;
    
27. top_tb.rx_dv <= 1'b0;
    
28. while(top_tb.rst_n)
    
29. @(posedge top_tb.clk);
    
30. for(int i = 0; i < 256; i++)begin
    
31. @(posedge top_tb.clk);
    
32. top_tb.rxd <= $urandom_range(0, 255);
    
33. top_tb.rx_dv <= 1'b1;
    
34. `uvm_info("my_driver", "data is drived", UVM_LOW)
    
35. end
    
36. @(posedge top_tb.clk);
    
37. top_tb.rx_dv <= 1'b0;
    
38. endtask
    
39. 
    
40. dut my_dut(.clk(clk),
    
41. .rst_n(rst_n),
    
42. .rxd(rxd),
    
43. .rx_dv(rx_dv),
    
44. .txd(txd),
    
45. .tx_en(tx_en));
    
46. 
    
47. initial begin
    
48. my_driver drv;
    
49. drv = new("drv", null);
    
50. drv.main_phase(null);
    
51. // $finish();
    
52. // rxd = 200;
    
53. // rx_dv = 0;
    
54. // @(posedge rst_n);
    
55. // rxd = 255;
    
56. // rx_dv = 1;
    
57. end
    
58. 
    
59. initial begin
    
60. clk = 0;
    
61. forever begin
    
62. #100 clk = ~clk;
    
63. end
    
64. end
    
65. 
    
66. initial begin
    
67. rst_n = 1'b0;
    
68. #1000;
    
69. rst_n = 1'b1;
    
70. end
    
71. 
    
72. endmodule

1. `ifndef MY_DRIVER__SV
   
2. `define MY_DRIVER__SV
   
3. class my_driver extends uvm_driver;
   
4. 
   
5. function new(string name = "my_driver", uvm_component parent = null);
   
6. super.new(name, parent);
   
7. endfunction
   
8. extern virtual task main_phase(uvm_phase phase);
   
9. endclass
   
10. 
    
11. task my_driver::main_phase(uvm_phase phase);
    
12. top_tb.rxd <= 8'b0;
    
13. top_tb.rx_dv <= 1'b0;
    
14. while(！top_tb.rst_n)
    
15. @(posedge top_tb.clk);
    
16. for(int i = 0; i < 256; i++)begin
    
17. @(posedge top_tb.clk);
    
18. top_tb.rxd <= $urandom_range(0, 255);
    
19. top_tb.rx_dv <= 1'b1;
    
20. `uvm_info("my_driver", "data is drived", UVM_LOW)
    
21. end
    
22. @(posedge top_tb.clk);
    
23. top_tb.rx_dv <= 1'b0;
    
24. endtask
    
25. `endif

1. setUVM_DPI_HOME/opt/mentor_graphics/questa/10.3a/questasim/uvm-1.1d/linux_x86_64
   
2. vlib work
   
3. vmap work
   
4. vlog+incdir+/opt/mentor_graphics/questa/10.3a/questasim/verilog_src/uvm-1.1d/src -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPFtop_tb.sv
   
5. vlog+incdir+/opt/mentor_graphics/questa/10.3a/questasim/verilog_src/uvm-1.1d/src -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPFdut.sv
   
6. vlog+incdir+/opt/mentor_graphics/questa/10.3a/questasim/verilog_src/uvm-1.1d/src -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPFmy_driver.sv
   
7. vsim-ldflags "-lregex" -t 1ns -c -sv_lib $UVM_DPI_HOME/uvm_dpi -voptargs=+acc -L lpm_ver -L altera_mf_ver -L altera_ver -L stratixv_ver work.top_tb
   
8. 
   
9. set StdArithNoWarnings 1
   
10. set NumericStdNoWarnings 1

试试先编译my_driver.sv，再编译top_tb.sv看看?

效果差不多，error信号如下

1. # ** Error: my_driver.sv(3): near "uvm_driver": syntax error, unexpected IDENTIFIER
   
2. # ** Error: my_driver.sv(3): Error in class extension specification.

`include "uvm_pkg.sv"
`include "uvm_macros.svh"
加到my_driver.sv里边试试

谢谢，这下可以了