一个使用VCS后仿真的问题，希望大侠可以帮忙，不是太好解决，谢谢：）

目前在后仿真时遇到一个问题设计所有寄存器的negtive check，暂以DFCNQD1BWP7T寄存器为例，该寄存器model如下：

1. `celldefine
   
2. module DFCNQD1BWP7T (D, CP, CDN, Q);
   
3. input D, CP, CDN;
   
4. output Q;
   
5. reg notifier;
   
6. `ifdef NTC
   
7. // Reserve for NTC.
   
8. `ifdef RECREM
   
9. // Reserve for RECREM.
   
10. wireCDN_d ;
    
11. buf(CDN_i, CDN_d);
    
12. `else
    
13. // Reserve for non RECREM.
    
14. buf(CDN_i, CDN);
    
15. `endif
    
16. wire D_d, CP_d ;
    
17. pullup(SDN);
    
18. tsmc_dff (Q_buf, D_d, CP_d, CDN_i, SDN, notifier);
    
19. buf(Q, Q_buf);
    
20. `else
    
21. // Reserve for non NTC.
    
22. buf(CDN_i, CDN);
    
23. pullup(SDN);
    
24. tsmc_dff (Q_buf, D, CP, CDN_i, SDN, notifier);
    
25. buf(Q, Q_buf);
    
26. `endif
    
27. 
    
28. 
    
29. 
    
30. // Timing logics defined for default constraint check
    
31. buf(CP_check, CDN_i);
    
32. buf(D_check, CDN_i);
    
33. `ifdef TETRAMAX
    
34. `else
    
35. tsmc_xbuf (CP_DEFCHK, CP_check, 1'b1);
    
36. tsmc_xbuf (D_DEFCHK, D_check, 1'b1);
    
37. `endif
    
38. 
    
39. `ifdef TETRAMAX
    
40. `else
    
41. specify
    
42. if (CP == 1'b1 && D == 1'b1)
    
43. (negedge CDN => (Q+:1'b0)) = (0, 0);
    
44. if (CP == 1'b1 && D == 1'b0)
    
45. (negedge CDN => (Q+:1'b0)) = (0, 0);
    
46. if (CP == 1'b0 && D == 1'b1)
    
47. (negedge CDN => (Q+:1'b0)) = (0, 0);
    
48. if (CP == 1'b0 && D == 1'b0)
    
49. (negedge CDN => (Q+:1'b0)) = (0, 0);
    
50. ifnone (negedge CDN => (Q+:1'b0)) = (0, 0);
    
51. (posedge CP => (Q+)) = (0, 0);
    
52. $width (negedge CDN, 0, 0, notifier);
    
53. $width (posedge CP &&& CP_DEFCHK, 0, 0, notifier);
    
54. $width (negedge CP &&& CP_DEFCHK, 0, 0, notifier);
    
55. `ifdef NTC
    
56. `ifdef RECREM
    
57. $setuphold (posedge CP &&& D_DEFCHK, posedge D, 0, 0, notifier,,, CP_d, D_d);
    
58. $setuphold (posedge CP &&& D_DEFCHK, negedge D, 0, 0, notifier,,, CP_d, D_d);
    
59. $recrem (posedge CDN, posedge CP, 0,0, notifier, , , CDN_d, CP_d);
    
60. `else
    
61. $setuphold (posedge CP &&& D_DEFCHK, posedge D, 0, 0, notifier,,, CP_d, D_d);
    
62. $setuphold (posedge CP &&& D_DEFCHK, negedge D, 0, 0, notifier,,, CP_d, D_d);
    
63. $recovery (posedge CDN, posedge CP, 0, notifier);
    
64. $hold (posedge CP, posedge CDN, 0, notifier);
    
65. `endif
    
66. `else
    
67. $setuphold (posedge CP &&& D_DEFCHK, posedge D, 0, 0, notifier);
    
68. $setuphold (posedge CP &&& D_DEFCHK, negedge D, 0, 0, notifier);
    
69. $recovery (posedge CDN, posedge CP, 0, notifier);
    
70. $hold (posedge CP, posedge CDN, 0, notifier);
    
71. `endif
    
72. endspecify
    
73. `endif
    
74. endmodule
    
75. `endcelldefine

后仿环境使用VCS 2009.06，当仿真时不加+neg_tchk选项时，反标时报如下错误：

1. Warning-[SDFCOM_NNTC] Need timing check option +neg_tchk
   
2. /home/yuanq/pnd_bb_chip/simulation/pnd_bb_chip_wcs.sdf, 109222
   
3. module: DFCNQD2BWP7T, "instance: tb_bb_psim.U_pnd_bb_chip.u_BD2_Channel.IF_L1_reg_1_"
   
4. SDF Error: Negative RECOVERY value replaced by 0.
   
5. Add +neg_tchk to consider Negative delay value.
   
6. 
   
7. 
   
8. Warning-[SDFCOM_NNTC] Need timing check option +neg_tchk
   
9. /home/yuanq/pnd_bb_chip/simulation/pnd_bb_chip_wcs.sdf, 109227
   
10. module: DFCNQD2BWP7T, "instance: tb_bb_psim.U_pnd_bb_chip.u_BD2_Channel.IF_L1_reg_1_"
    
11. SDF Error: Negative HOLD value replaced by 0.
    
12. Add +neg_tchk to consider Negative delay value.

为了检查negtive延迟，增加+neg_tchk，反标仍有错误：

1. Warning-[SDFCOM_NL] Negative Limit on Simple TC
   
2. ../../nl/pnd_bb_chip_wcs.sdf, 113120
   
3. module: DFCNQD1BWP7T, "instance: tb_bb_psim_max_inf_t.U_pnd_bb_chip.u_BD2_Channel.i_TIMEBASE_GEN.flag_armed_reg"
   
4. SDF Warning: Negative limit cannot be used in simple timing check, it's
   
5. replaced by 0.
   
6. Please use $recrem ..

根据寄存器model定义了NTC和RECREM以便调用$recrem系统函数，但是定义以上两个宏后仍然报如下错误：

1. Warning-[SDFCOM_CFTC] Cannot find timing check
   
2. ../../nl/pnd_bb_chip_wcs.sdf, 113119
   
3. module: DFCNQD1BWP7T, "instance: tb_bb_psim_max.U_pnd_bb_chip.u_BD2_Channel.i_TIMEBASE_GEN.flag_armed_reg"
   
4. SDF Warning: Cannot find timing check $hold(posedge CP,posedge CDN,...)

TSMC的库?同问啊！

这种问题也有同问呀！
问题已经解决，是pt提取sdf的问题，一是注意pt的版本，二是注意是否输出negetive参数。

问一下，哪个版本的PT存在问题?
另外你所说的是否提取Negative参数，是提取还是不提取?

加+neg_tchk选项以后可以注意到"SDF Error"变成"SDF Warning"了。
当然也可以让STA工具写SDF的时候去掉负的timing check, 前提是这些timing没问题，或者你只是在调试阶段。

学习学习

学习学习

我的sdf文件是用dc生成的。
怎么办?

同问。 我的sdf目前也是dc的加上neg_tchk 好多错误都没有了 请问为何。、

今天也遇到sdf反标的问题。库里面是$recovery和$removal，但后仿说没找到$hold...
后来找到原因：sdf2.1版本不支持removal，换sdf3.0就好了。
pt的write_sdf加-version 3.0的选项。