model_sim编译UVM文件后run时遇到了fatal error
时间：10-02
整理：3721RD
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model_sim编译UVM文件后遇到的fatal error:
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM]questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test spi_reg_test...
# ** Fatal: (SIGSEGV) Bad handle or reference.
#Time: 0 psIteration: 15Process: /uvm_pkg::uvm_phase::m_run_phases/#FORK#1765_7ba718a File: ../sv_exe/top.svh
请问解决办法是什么?谢谢！
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM]questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test spi_reg_test...
# ** Fatal: (SIGSEGV) Bad handle or reference.
#Time: 0 psIteration: 15Process: /uvm_pkg::uvm_phase::m_run_phases/#FORK#1765_7ba718a File: ../sv_exe/top.svh
请问解决办法是什么?谢谢！
这个应该是你写的spi_reg_test有问题，是SV的空指针，跟UVM没有多大关系。