Random Sequence Generation问题，编译有点问题，望大家帮忙看看

1. program p;
   
2. initial begin
   
3. randsequence()
   
4. main : repeat (10) TOP;
   
5. TOP: RJ {$display("");};
   
6. RJ: rand join (1.0) S1 S2 S3;
   
7. S1 : A B;
   
8. S2 : C D;
   
9. S3 : E F G;
   
10. A : {$write ("A");};
    
11. B : {$write ("B");};
    
12. C : {$write ("C");};
    
13. D : {$write ("D");};
    
14. E : {$write ("E");};
    
15. F : {$write ("F");};
    
16. G : {$write ("G");};
    
17. endsequence
    
18. end
    
19. endprogram

1. irun: 10.20-s100: (c) Copyright 1995-2011 Cadence Design Systems, Inc.
   
2. TOOL:irun10.20-s100: Started on Sep 26, 2013 at 12:47:57 CST
   
3. irun
   
4. -sv
   
5. -seed random
   
6. RSG.sv
   
7. Recompiling... reason: file './RSG.sv' is newer than expected.
   
8. expected: Thu Sep 26 12:36:35 2013
   
9. actual:Thu Sep 26 12:47:56 2013
   
10. file: RSG.sv
    
11. RJ : rand join (1.0) S1 S2 S3
    
12. |
    
13. ncvlog: *E,RSNOPROD (RSG.sv,6|20): randsequence production has no production items [SystemVerilog LRM, randsequence].
    
14. RJ : rand join (1.0) S1 S2 S3
    
15. |
    
16. ncvlog: *E,RSSEMICLN (RSG.sv,6|20): Expected semicolon after a randsequence production [SystemVerilog LRM, randsequence].
    
17. RJ : rand join (1.0) S1 S2 S3
    
18. |
    
19. ncvlog: *E,RSENDSEQ (RSG.sv,6|25): randsequence must end with "endsequence".
    
20. RJ : rand join (1.0) S1 S2 S3
    
21. |
    
22. ncvlog: *E,NOTSTT (RSG.sv,6|27): expecting a statement [9(IEEE)].
    
23. RJ : rand join (1.0) S1 S2 S3
    
24. |
    
25. ncvlog: *E,MISEXX (RSG.sv,6|37): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
    
26. RJ : rand join (1.0) S1 S2 S3
    
27. |
    
28. ncvlog: *E,MISEXX (RSG.sv,6|40): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
    
29. S1 : A B;
    
30. |
    
31. ncvlog: *E,MISEXX (RSG.sv,7|13): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
    
32. S1 : A B;
    
33. |
    
34. ncvlog: *E,NOLABL (RSG.sv,7|13): Labels are not supported on this statement type.
    
35. S1 : A B;
    
36. |
    
37. ncvlog: *E,MISEXX (RSG.sv,7|19): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
    
38. S2 : C D;

使用vcs2012.09和ius12.20都可以编译通过并仿真。
不过还是有个针对rand join (1.0) ... 中的1.0的warning，没用过这个，不太清楚为什么还有wanrning。

莫非是版本问题，我用的是irun 2011跑的，会不会是版本不支持呢?

有这个可能性。仿真器版本不同，对systemverilog标准实现的程度是不一样的。
另外，你用的不叫irun 2011，而是ius10.20。

哦，多谢！

哦，感谢，的确是ius10.20-s100