FPGAXC2S15不稳定，为何？
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity XC2S15 is
Port (
CP:IN STD_LOGIC ;--CLK
A: IN STD_LOGIC_VECTOR(10 DOWNTO 0); --A0-A10 ADDISA总线的11位地址线
IOR : IN STD_LOGIC ; --Read Signal
IOW : IN STD_LOGIC ; --Writ Signal
AEN : IN STD_LOGIC ; --Add Free
IO16 : OUT STD_LOGIC; --16IO
CP5:OUT STD_LOGIC;--
PLUSE: OUT STD_LOGIC;
I: INOUT STD_LOGIC_VECTOR(15 DOWNTO 0)--D0-D15
);
end XC2S15;
architecture Behavioral of XC2S15 is
SIGNAL BUF2:STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL Y7,Y8,Y9:STD_LOGIC;
SIGNAL ADD: STD_LOGIC_VECTOR (13 DOWNTO 0); --ADD+IOR+IOW+AED
SIGNAL OUTPUT : STD_LOGIC_VECTOR (4 DOWNTO 0); --OUTPUT CONECL
SIGNAL BUFX2: STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL STAGESBUF:STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL ORDER:STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL QN :STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL CP1,CP2,CP4,RST:STD_LOGIC;
SIGNAL COUNTER :STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL DLY :STD_LOGIC;
SIGNAL SINX:STD_LOGIC;
SIGNAL XAXA:STD_LOGIC;
begin
ADD(13)<=A(10); --\
ADD(12)<=A(9);--|
ADD(11)<=A(8);--|
ADD(10)<=A(7);--|
ADD(9)<=A(6);--|
ADD(8)<=A(5);--|
ADD(7)<=A(4);--> ADD
ADD(6)<=A(3);--|
ADD(5)<=A(2);--|
ADD(4)<=A(1);--|
ADD(3)<=A(0);--|
ADD(2)<=IOR;--|
ADD(1)<=IOW;--|
ADD(0)<=AEN; --/
OUTPUT<="00010" WHEN ADD="01100000000010" ELSE --0X300--read BUFX status
"00100" WHEN ADD="01100000010100" ELSE --0X302--write stages
"01000" WHEN ADD="01100001010100" ELSE --0X30A
"00001" ;
Y9<=OUTPUT(3);--写脉冲数
Y8<=OUTPUT(2);--写分频数
Y7<=OUTPUT(1);--读状态
IO16<=OUTPUT(0);--ISA总线16位数据选择信号，0有效
PROCESS(Y7)
BEGIN
IFY7='1' THEN--BUF2为BUFX2空与满的标志，I是ISA16位数据总线
I<=BUF2;
ELSE
I<="ZZZZZZZZZZZZZZZZ";
END IF;
END PROCESS;
PROCESS(Y9,CP2,CP)
VARIABLE BUFX2 :STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
IFY9='1' THEN--写脉冲数BUFX2减一次，XAXA翻转一次，BUFX2减两次，PLUSE输出一个脉冲
BUFY2:=I;
ELSIF BUFX2/="0000000000000000" THEN
IF CP2' EVENT AND CP2='1' THEN--根据任意分频数分出的频率CP2进行
BUFX2:=BUFX2-1;
XAXA<=NOT XAXA;
END IF;
SINX<='1';
ELSE
SINX<='0';
END IF;
IF BUFX2="0000000000000000" THEN
BUF2<="1010101010101010";
ELSE
BUF2<="0000000000000000";
END IF;
END PROCESS;
PROCESS(Y8)
BEGIN
IFY8='1' THEN
STAGESBUF<=I;
END IF;
END PROCESS;
PROCESS(CP,RST)--10分频CP=10MCP1=1M
BEGIN
IF RST='1'THEN
QN<="0000";
ELSIF CP' EVENT AND CP='1' THEN
QN<=QN+1;
END IF;
END PROCESS;
RST<='1' WHEN QN=10 ELSE
'0';
CP1<=QN(2);
PROCESS(CP1)--根据STAGESBUF任意分频CP2=CP1 * (STAGESBUF/32767)
BEGIN
IF CP1' EVENT AND CP1='1' THEN
DLY<=COUNTER(15);
COUNTER<=COUNTER+STAGESBUF;
END IF;
CP2<=(COUNTER(15) XOR DLY) AND NOT CP1;
CP5<=CP1;
END PROCESS;
PLUSE<=XAXA WHEN SINY='1' ELSE--PLUSE为输出的脉冲
'0';
end Behavioral;
通过ISA总线读0X300，假如为0XAAAA，表示BUFX2为空，通过0X302写入STAGESBUF，通过0X30A写入BUFX2
就可以看到PLUSE输出口有以CP2的频率输出BUFX2/2个等宽脉冲。
我每次以2K的频率来读0X300，频率不高，我的CP被自动指定为全局时钟，我用IBUFG+BUFG。
运行一次或几百次都没有问题，但连续运行几个小时就要出现脉冲数不准的现相。没有规律，不知道是为什么
?
我用ISE6.1进行综合、布线，有没有问题?是不是因为XST的综合出问题?
FPGAXC2S15不稳定，为何?
WARNING:Xst:819 - E:/XC2S15XY/XC2S15(3)1/xc2s/XC2S151.vhd line 141: The following signals are missing in the process sensitivity list：
INFO:Xst:1304 - Contents of register <I<12>> in unit <xc2s151> never changes during circuit operation. The register is replaced by logic。
WARNING:Xst:1710 - FF/Latch<Mtridata_I_0> (without init value) is constant in block <xc2s151>.
这三个WARNING是什么意思?会不会影响稳定性?
FPGAXC2S15不稳定，为何?
帮帮忙！
难道XLINIX的FPGAISE没有人用?
FPGAXC2S15不稳定，为何?
我用xlinx fpga但是我不用ise的集成环境
我一般是：采用fpga compiler 或者 synplify 来直接综合.然后，在使用批处理来执行的。这样效率更高。
以上的警告，分别是说：
在你的敏感想里面缺少相应的信号。
在工作时，寄存器I<12>，将不会翻转，所以被优化掉了，这是你的设计友问题。
FPGAXC2S15不稳定，为何?
在工作时，寄存器I<12>，将不会翻转，所以被优化掉了，这是你的设计友问题。
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我的 I 是双向数据总线，为何没有翻转?I<0> TO I<15> 都被优化掉。
高人，万分感激！
FPGAXC2S15不稳定，为何?
我综合时出现如下警告，不知道是什么意思?请高人指点！
*Low Level Synthesis*
=========================================================================
WARNING:Xst:1710 - FF/Latch<_n0011_0> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and _n0011<2> _n0011<2> signal will be lost.
WARNING:Xst:1710 - FF/Latch<_n0011_2> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and _n0011<4> _n0011<4> signal will be lost.
WARNING:Xst:1710 - FF/Latch<_n0011_4> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and _n0011<6> _n0011<6> signal will be lost.
WARNING:Xst:1710 - FF/Latch<_n0011_6> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and _n0011<8> _n0011<8> signal will be lost.
WARNING:Xst:1710 - FF/Latch<_n0011_8> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and _n0011<10> _n0011<10> signal will be lost.
WARNING:Xst:1710 - FF/Latch<_n0011_10> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and _n0011<12> _n0011<12> signal will be lost.
WARNING:Xst:1710 - FF/Latch<_n0011_12> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and Mtridata_I<0> Mtridata_I<0> signal will be lost.
WARNING:Xst:1710 - FF/Latch<Mtridata_I_0> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and Mtridata_I<2> Mtridata_I<2> signal will be lost.
WARNING:Xst:1710 - FF/Latch<Mtridata_I_2> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and Mtridata_I<4> Mtridata_I<4> signal will be lost.
WARNING:Xst:1710 - FF/Latch<Mtridata_I_4> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and Mtridata_I<6> Mtridata_I<6> signal will be lost.
WARNING:Xst:1710 - FF/Latch<Mtridata_I_6> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and Mtridata_I<8> Mtridata_I<8> signal will be lost.
WARNING:Xst:1710 - FF/Latch<Mtridata_I_8> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and Mtridata_I<10> Mtridata_I<10> signal will be lost.
WARNING:Xst:1710 - FF/Latch<Mtridata_I_10> (without init value) is constant in block <xc2s151>.
WARNING:Xst:638 - in unit xc2s151 Conflict on KEEP property on signal _n0011<0> and Mtridata_I<12> Mtridata_I<12> signal will be lost.
WARNING:Xst:1710 - FF/Latch<Mtridata_I_12> (without init value) is constant in block <xc2s151>.
I 是我的16位的双向数据总线。
WARNING:Xst:1710 - FF/Latch (without init value) is constant in block .
可能是你的I/O口有冲突，仔细看程序吧