求助综合通过，但是仿真波形出不来，reset无法赋值

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity frequence_controlled_word_1 is
port(clk:instd_logic;
RST:instd_logic;
frequence_controlled_word:outstd_logic_vector(29 downto 0)
);
end frequence_controlled_word_1;

architecture behave of frequence_controlled_word_1 is

signal f:std_logic_vector(29 downto 0);
signal change_amount:std_logic_vector(29 downto 0);
signal num_of_step:std_logic_vector(29 downto 0);
signal sign:boolean;

begin

process(RST,clk)
begin
if (RST = '1') then
sign <= false;
elsif (clk = '1' and clk'event) then
if (sign = false) then
f <= f - change_amount;
sign <= true;
else
f <= f + change_amount;
sign <= false;
end if;
end if;
end process;

process(RST,clk)
begin
if (RST = '1') then
num_of_step <="000000000000000000000000000000";
f <="001000110110100011011010001110";--f0;
elsif (clk = '1' and clk'event) then
if(num_of_step="000000000000000000101110111001") then
num_of_step <= "000000000000000000000000000000";
f <= "001000110110100011011010001110";--f0;
else
num_of_step <= num_of_step + "000000000000000000000000000001";
end if;
end if;
end process;

process(num_of_step)
begin
change_amount<=num_of_step;
change_amount(29 downto 11) <= change_amount(18 downto 0);
change_amount(10 downto 0)<= "00000000000";
end process;

process(f)
begin
frequence_controlled_word<=f;
end process;
end behave;
这是我编得一个DDS频率控制字程序，要求频率以初值为中心上下浮动，扫描到正负最大值后再回到初值，如此循环。仿真发现reset为1时，frequence_controlled_word无法赋值，请教大侠如何改正。

补充一下，change_amount是每次频率字的改变量，它是在num_of_step的基础上乘以2048得到的，即做移11位。

frequence_controlled_word在reset=1时也全是u，当reset变为0时，全部变成X了

不能在两个process中对同一信号赋值
代码中的f

楼上可能说得对，在verilog这种情景也还是不允许
得

谢谢atuhappy和liumeco，我加了一个中间变量，存储f的值，用时钟上升沿控制赋值，相当于作了一个延时，结果波形就出来了。