大家帮我仿真一下这个吧
时间:10-02
整理:3721RD
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遇到一个难题,使用modelsimSE5。8仿真下面的程序时,总是失败,请教各位,帮我仿真一下吧,不胜感激,继续波形,我的邮箱xiaomai8365@hotmail.com
module communication(clk,err,out1,out2,signal,tail_crc,wrong);
input clk;
input err;
output[4:0]tail_crc;
output[11:0]out1;
output[11:0]out2;
output signal;
output wrong;
reg[4:0]tail_crc;
reg[16:0]temp1,temp2;
reg[11:0]out1,out2;
reg[11:0]buf1,buf2;
reg[16:0]shift;
reg hx,hy,ha,hb,confim;
reg first;
reg signal,wrong;
reg[3:0] i1,i2,i3;
reg[5:0] count;
always@(posedge clk)
begin
if(! first)shift=16'h8000;
first=1;
if(! hx)
begin
hy=0;
i1=i1+1;
shift=shift>>1;
shift[16]=shift[15]^shift[12];
if (!shift[16:13]) shift[16:13]=4'b1000;
if (i1==4'hc) begin hy=1;i1=0;end
end
end
always@(posedge clk)
begin
if(!confim)hx=0;
else hx=1;
if(hy)
begin
hx=1;
hb=0;
out1=shift;
buf1=shift;
temp1[16:5]=buf1;
if(buf1[11]) buf1[11:6]=buf1[11:6]^6'b110101;
if(buf1[10]) buf1[10:5]=buf1[10:5]^6'b110101;
if(buf1[9]) buf1[9:4]=buf1[9:4]^6'b110101;
if(buf1[8]) buf1[8:3]=buf1[8:3]^6'b110101;
if(buf1[7]) buf1[7:2]=buf1[7:2]^6'b110101;
if(buf1[6]) buf1[6:1]=buf1[6:1]^6'b110101;
if(buf1[5]) buf1[5:0]=buf1[5:0]^6'b110101;
temp1[4:0]=buf1[4:0];
tail_crc=buf1[4:0];
if(!ha) hb=1;
end
end
always@(negedge clk)
begin
if(hb)
begin
ha=1;
temp2=temp1;
if(err) temp2[16]=~temp2[16];
buf2=temp2[16:5];
if(buf2[11]) buf2[11:6]=buf2[11:6]^6'b110101;
if(buf2[10]) buf2[10:5]=buf1[10:5]^6'b110101;
if(buf2[9]) buf2[9:4]=buf2[9:4]^6'b110101;
if(buf2[8]) buf2[8:3]=buf2[8:3]^6'b110101;
if(buf2[7]) buf2[7:2]=buf2[7:2]^6'b110101;
if(buf2[6]) buf2[6:1]=buf2[6:1]^6'b110101;
if(buf2[5]) buf2[5:0]=buf2[5:0]^6'b110101;
if (temp2[4:0]^buf2[4:0])
begin
signal=1;
confim=1;
temp2=temp1;
count=count+1;
out2=0;
if(count>32)
begin
count=40;
wrong=1;
end
end
else
begin
wrong=0;
count=0;
signal=0;
confim=0;
out2=temp2[16:5];
end
ha=0;
end
end
endmodule
module communication(clk,err,out1,out2,signal,tail_crc,wrong);
input clk;
input err;
output[4:0]tail_crc;
output[11:0]out1;
output[11:0]out2;
output signal;
output wrong;
reg[4:0]tail_crc;
reg[16:0]temp1,temp2;
reg[11:0]out1,out2;
reg[11:0]buf1,buf2;
reg[16:0]shift;
reg hx,hy,ha,hb,confim;
reg first;
reg signal,wrong;
reg[3:0] i1,i2,i3;
reg[5:0] count;
always@(posedge clk)
begin
if(! first)shift=16'h8000;
first=1;
if(! hx)
begin
hy=0;
i1=i1+1;
shift=shift>>1;
shift[16]=shift[15]^shift[12];
if (!shift[16:13]) shift[16:13]=4'b1000;
if (i1==4'hc) begin hy=1;i1=0;end
end
end
always@(posedge clk)
begin
if(!confim)hx=0;
else hx=1;
if(hy)
begin
hx=1;
hb=0;
out1=shift;
buf1=shift;
temp1[16:5]=buf1;
if(buf1[11]) buf1[11:6]=buf1[11:6]^6'b110101;
if(buf1[10]) buf1[10:5]=buf1[10:5]^6'b110101;
if(buf1[9]) buf1[9:4]=buf1[9:4]^6'b110101;
if(buf1[8]) buf1[8:3]=buf1[8:3]^6'b110101;
if(buf1[7]) buf1[7:2]=buf1[7:2]^6'b110101;
if(buf1[6]) buf1[6:1]=buf1[6:1]^6'b110101;
if(buf1[5]) buf1[5:0]=buf1[5:0]^6'b110101;
temp1[4:0]=buf1[4:0];
tail_crc=buf1[4:0];
if(!ha) hb=1;
end
end
always@(negedge clk)
begin
if(hb)
begin
ha=1;
temp2=temp1;
if(err) temp2[16]=~temp2[16];
buf2=temp2[16:5];
if(buf2[11]) buf2[11:6]=buf2[11:6]^6'b110101;
if(buf2[10]) buf2[10:5]=buf1[10:5]^6'b110101;
if(buf2[9]) buf2[9:4]=buf2[9:4]^6'b110101;
if(buf2[8]) buf2[8:3]=buf2[8:3]^6'b110101;
if(buf2[7]) buf2[7:2]=buf2[7:2]^6'b110101;
if(buf2[6]) buf2[6:1]=buf2[6:1]^6'b110101;
if(buf2[5]) buf2[5:0]=buf2[5:0]^6'b110101;
if (temp2[4:0]^buf2[4:0])
begin
signal=1;
confim=1;
temp2=temp1;
count=count+1;
out2=0;
if(count>32)
begin
count=40;
wrong=1;
end
end
else
begin
wrong=0;
count=0;
signal=0;
confim=0;
out2=temp2[16:5];
end
ha=0;
end
end
endmodule
大家帮我仿真一下这个吧
你又不把错误提示贴出来,也不说这是什么东西,谁有空帮你仿?
大家帮我仿真一下这个吧
是啊,你应该把问题说清楚点………
大家帮我仿真一下这个吧
老实说,这个电路有点不像是手工写的,倒像是用图形化的软件生成的,比较乱!
大家帮我仿真一下这个吧
写的太不规范了,看得费劲。