helping

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dctram is port(
-- Inputs
clk : in std_logic; -- Clock, async reset
en, we : in std_logic; -- Sync enable, write enable
ar : in std_logic_vector(5 downto 0); -- Read address
aw : in std_logic_vector(5 downto 0); -- Write address
din : in std_logic_vector(15 downto 0); -- Data input bus
-- Outputs
dout : out std_logic_vector(15 downto 0) -- Data output bus
);
end dctram;
architecture beh of dctram is
type mram is array (63 downto 0) of std_logic_vector(15 downto 0);

shared variable mem : mram; -- Memory array 64x16

begin
-- Dual port RAM model
process(clk) begin
if clk'event and clk = '1' then
-- Memory is written and read synchronoulsy
-- when enabled
if en = '1' then
-- Write port
if we = '1' then
mem(conv_integer(aw)) := din;
end if;
-- Read port
dout <= mem(conv_integer(ar));
end if;
end if;
end process;
end beh;
--****************************************************--
--********modelsim error imply************************--
--****************************************************--
#vcom -workwork ram1/avgram.vhd
# vcom -workwork ram1/dctram.vhd
# Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity dctram
# -- Compiling architecture beh of dctram
# ** Error: ram1/dctram.vhd(45): near "shared": expecting: BEGIN
# ERROR: C:/Modeltech_5.7d/win32/vcom failed.
# Error in macro F:\mpeg4\MPEG-4\tb\compile.do line 90
# C:/Modeltech_5.7d/win32/vcom failed.
#while executing
# "vcom -workwork ram1/dctram.vhd
--*****************************************************--

helping
type mram is array (63 downto 0) of std_logic_vector(15 downto 0);
＝＝＝＝＝
这句type的定义语法有问题。
subtype word is std_logic_vector(15 downto 0);
type mram is array (integer range 0 to 63) of word;
mem也最好直接定义为signal。