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this is vhdl model:if clk'event and clk='1' then
if I convert this model to verilog :
if (clk == 1'b1)....

asking for helping
[这个贴子最后由atuhappy在 2004/06/15 08:43pm 第 1 次编辑]
always@(posedge clk)
beign
end

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thank you！

asking for helping
By the way ,I'm afraidyou shouldsubstitute your title for asking for help！