CC430接收中断出错
最近用CC430F5137做了两块实验板，实现数据收发，接收端接收到数据后，串口发送，在pc端利用串口助手查看数据。
现在的问题是，数据接收一段时间后，程序就死了，看着像是进不去接收中断了，请问有人有相关的经验指点一下吗？
具体的程序如下：
#define PACKET_LEN (0x06) // PACKET_LEN <= 61
#define CRC_LQI_IDX (PACKET_LEN+1) // Index of appended LQI, checksum
#define CRC_OK (BIT7) // CRC_OK bit
#define PATABLE_VAL (0xC6) // 10 dBm output
#define CPU_F ((double)32768)
#define delay_ms(x) __delay_cycles((long)(CPU_F*(double)x/1000.0))
extern RF_SETTINGS rfSettings;
RF_SETTINGS rfSettings = {
0x06, // FSCTRL1 Frequency synthesizer control.//
0x00, // FSCTRL0 Frequency synthesizer control.
0x10, // FREQ2 Frequency control word, high byte.//
0xA7, // FREQ1 Frequency control word, middle byte.//
0x62, // FREQ0 Frequency control word, low byte.//
0xCA, // MDMCFG4 Modem configuration.//
0x83, // MDMCFG3 Modem configuration.//
0x13, // MDMCFG2 Modem configuration.//
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.//
0x34, // DEVIATN Modem deviation setting (when FSK modulation is enabled).//
0x56, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end TX configuration.
0x10, // MCSM0 Main Radio Control State Machine configuration.//
0x16, // FOCCFG Frequency Offset Compensation Configuration.//
0x6C, // BSCFG Bit synchronization Configuration.//
0x43, // AGCCTRL2 AGC control.
0x40, // AGCCTRL1 AGC control.
0x91, // AGCCTRL0 AGC control.
0xE9, // FSCAL3 Frequency synthesizer calibration.//
0x2A, // FSCAL2 Frequency synthesizer calibration.//
0x00, // FSCAL1 Frequency synthesizer calibration.//
0x1F, // FSCAL0 Frequency synthesizer calibration.//
0x59, // FSTEST Frequency synthesizer calibration.
0x81, // TEST2 Various test settings.//
0x35, // TEST1 Various test settings.//
0x09, // TEST0 Various test settings.//
0x47, // FIFOTHR RXFIFO and TXFIFO thresholds.//
0x29, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0 GDO0 output pin configuration. Refer to SmartRF Studio User Manual for detailed pseudo register explanation.
0x04, // PKTCTRL1 Packet automation control.
0x04, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0x06 // PKTLEN Packet length.
};
unsigned char PacketReceived;
unsigned char Receiving = 0;
unsigned char RxBuffer[PACKET_LEN+2];
unsigned char RxBufferLength = 0;
unsigned char SlaveStepInfo[PACKET_LEN];
void main( void )
{
// Stop watchdog timer to prevent time out reset
WDTCTL = WDTPW + WDTHOLD;
// Increase PMMCOREV level to 2 for proper radio operation
SetVCore(2);
ResetRadioCore();
InitRadio();
InitIO();
InitUART();
ReceiveOn();
Receiving = 1;
PacketReceived = 0;
while (1)
{
_EINT();
__no_operation();
if(PacketReceived)
{
P3OUT |= BIT4;
delay_ms(1000);
for( unsigned char i = 0; i < PACKET_LEN; i++)
{
SlaveStepInfo[i] = RxBuffer[i];
}
for(unsigned char j = 0; j < PACKET_LEN; j++)
{
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = SlaveStepInfo[j]; // TX -> RXed character
}
delay_ms(1000);
P3OUT &= ~BIT4;
PacketReceived = 0;
Receiving = 1;
ReceiveOn();
}
}
}
void InitIO(void)
{
// Initialize Port J
PJOUT = 0x00;
PJDIR = 0xFF;
// Set up LEDs
P3OUT &= ~(BIT4+BIT5);
P3DIR |= BIT4+BIT5;
}
void InitRadio(void)
{
// Set the High-Power Mode Request Enable bit so LPM3 can be entered
// with active radio enabled
PMMCTL0_H = 0xA5;
PMMCTL0_L |= PMMHPMRE_L;
PMMCTL0_H = 0x00;
WriteRfSettings(&rfSettings);
WriteSinglePATable(PATABLE_VAL);
}
void ReceiveOn(void)
{
RF1AIES |= BIT9; // Falling edge of RFIFG9
RF1AIFG &= ~BIT9; // Clear a pending interrupt
RF1AIE |= BIT9; // Enable the interrupt
// Radio is in IDLE following a TX, so strobe SRX to enter Receive Mode
Strobe( RF_SRX );
}
void ReceiveOff(void)
{
RF1AIE &= ~BIT9; // Disable RX interrupts
RF1AIFG &= ~BIT9; // Clear pending IFG
// It is possible that ReceiveOff is called while radio is receiving a packet.
// Therefore, it is necessary to flush the RX FIFO after issuing IDLE strobe
// such that the RXFIFO is empty prior to receiving a packet.
Strobe( RF_SIDLE );
Strobe( RF_SFRX );
}
#pragma vector=CC1101_VECTOR
__interrupt void CC1101_ISR(void)
{
switch(__even_in_range(RF1AIV,32)) // Prioritizing Radio Core Interrupt
{
case 0: break; // No RF core interrupt pending
case 2: break; // RFIFG0
case 4: break; // RFIFG1
case 6: break; // RFIFG2
case 8: break; // RFIFG3
case 10: break; // RFIFG4
case 12: break; // RFIFG5
case 14: break; // RFIFG6
case 16: break; // RFIFG7
case 18: break; // RFIFG8
case 20: // RFIFG9
if(Receiving) // RX end of packet
{
RF1AIE &= ~BIT9; // Disable RX interrupts
RF1AIFG &= ~BIT9; // Clear pending IFG
// Read the length byte from the FIFO
RxBufferLength = ReadSingleReg( RXBYTES );
ReadBurstReg(RF_RXFIFORD, RxBuffer, RxBufferLength);
// Stop here to see contents of RxBuffer
__no_operation();
// Check the CRC results
if(RxBuffer[CRC_LQI_IDX] & CRC_OK)
PacketReceived = 1; // Packet Received Sucessfully
Receiving = 0;
Strobe( RF_SIDLE );
Strobe( RF_SFRX );
}
break;
case 22: break; // RFIFG10
case 24: break; // RFIFG11
case 26: break; // RFIFG12
case 28: break; // RFIFG13
case 30: break; // RFIFG14
case 32: break; // RFIFG15
}
__bic_SR_register_on_exit(LPM3_bits);
}
Rx FIFO 有没有溢出？