cc1110 flash ，写不了数据

void Flash_DmaWrite( unsigned char *pFlashAddr, unsigned char *pSrcBuf, unsigned int Length ) {   dmaConfig.SRCADDRH  = ((unsigned int)pSrcBuf >> 8) & 0x00FF;     dmaConfig.SRCADDRL  = (unsigned int)pSrcBuf & 0x00FF;     dmaConfig.DESTADDRH = ((unsigned int)&X_FWDATA >> 8) & 0x00FF;     dmaConfig.DESTADDRL = (unsigned int)&X_FWDATA & 0x00FF;     dmaConfig.VLEN      = DMA_VLEN_USE_LEN;     dmaConfig.LENH      = (Length >> 8) & 0x00FF;     dmaConfig.LENL      =  Length & 0x00FF;     dmaConfig.WORDSIZE  = DMA_WORDSIZE_BYTE;     dmaConfig.TMODE     = DMA_TMODE_SINGLE;     dmaConfig.TRIG      = DMA_TRIG_FLASH;     dmaConfig.SRCINC    = DMA_SRCINC_1;     dmaConfig.DESTINC   = DMA_DESTINC_0;     dmaConfig.IRQMASK   = DMA_IRQMASK_DISABLE;     dmaConfig.M8        = DMA_M8_USE_8_BITS;     dmaConfig.PRIORITY  = DMA_PRI_HIGH;

    /* The DMA configuration data structure may reside at any location in      * unified memory space, and the address location is passed to the DMA      * through DMA0CFGH:DMA0CFGL.      */     DMA0CFGH = ((unsigned int)&dmaConfig >> 8) & 0x00FF;     DMA0CFGL = (unsigned int)&dmaConfig & 0x00FF;

    /* Waiting for the flash controller to be ready */     while (FCTL & FCTL_BUSY);

    /* Configuring the flash controller. Setings:      * FWT: 0x11 (default setting, matches 13 MHz clock frequency).      * FADDRH:FADDRL: point to the area in flash to write to - flashDataAddr.      */     FWT = 0x11;     FADDRH = (int)pFlashAddr >> 9;     FADDRL = ((int)pFlashAddr >> 1) & ~0xFF00;

    /* Erase the page that will be written to. */      Flash_StartErase();

    /* Wait for the erase operation to complete. */     while (FCTL & FCTL_BUSY);

    /* Arm the DMA channel, so that a DMA trigger will initiate DMA writing. */     DMAARM |= DMA_CHANNEL_0;            // Arm DMA channel 0

    /* Enable flash write. Generates a DMA trigger. Must be aligned on a 2-byte      * boundary and is therefor implemented in assembly.      */     Flash_StartWrite();

    /* Wait for DMA transfer to complete. */     while (!(DMAIRQ & DMAIRQ_DMAIF0));

    /* Wait until flash controller not busy. */     while (FCTL & (FCTL_BUSY | FCTL_SWBSY));

    /* By now, the transfer is completed, so the transfer count is reached.      * The DMA channel 0 interrupt flag is then set, so we clear it here.      */     DMAIRQ &= ~DMAIRQ_DMAIF0; }

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另外你排版看着乱。