PurePath中CC8530对AIC3254 IN1L/R旁通至HPL/R不成功
我的项目这样的：
CC8531板用作Master，双向音频流，Application Role：Dual stereo headset USB soundcard
CC8530+AIC3254 作Slave板，双向音频流, Application Role：Stereo headset
我想在Slave板使用AIC3254的IN1L/R 通过MicPGA和Mixer Amplifier 旁通至HPL/HPR,以实现IN1L/R的麦克输入与来自Master的音频流经DAC后在HPL/HPR混音。但在Slave板能够听到来自Master的音频，却得不到IN1L/R的麦克声音。不知道哪里有问题？
PurPath Wireless Configurator的Audio Device Customerization里，我对Configuration Sequences作如下更改（板子硬件确认是好的，且所有对AIC3254设置的参数，均在AIC3254EVM-U CS软件中调好，在AIC3254EVM-U CS中可以实现我们想要的混音功能。也作了Audio Device Defintion 文件更改，见附件，就是不行）：
#OFF to SR-Switch
# PIN RESET
p Reset 1 # Release the reset pin
# RESET
w 30 00 00 # Select register page 0
w 30 01 01 # I2C reset
# CLOCK SETTINGS
w 30 0B 81 # Power up the NDAC divider with value 1
w 30 0C 82 # Power up the MDAC divider with value 2
w 30 0D 00 # Program OSR for DAC to 128 (MSB)
w 30 0E 80 # Program OSR for DAC to 128 (LSB)
w 30 12 81 # Power up the NADC divider with value 1
w 30 13 82 # Power up the MADC divider with value 2
w 30 14 80 # Program OSR for ADC to 128
# DIGITAL INTERFACE
w 30 1B 00 # I2S, 16-bit, BCLK and WCLK are inputs
# PROCESSING BLOCK USAGE
w 30 3C 08 # Select DAC processing block PRB_P8
w 30 3D 01 # Select ADC processing block PRB_R1
# ANALOG POWER SUPPLY
w 30 00 01 # Select register page 1
w 30 01 08 # Disable internal crude AVDD before powering up the internal AVDD LDO
w 30 02 A1 # Enable internal analog LDO, analog blocks powered
w 30 0A 40 # Common mode set to 0.75V
# MICPGA DELAY, REFERENCE CHARGING AND HEADPHONE DE-POP
w 30 47 31 # MICPGA startup delay is 3 ms
w 30 7B 01 # Reference charging time is 40 ms
w 30 14 65 # HP driver power-up: 50 ms soft routing step time, 5.0 time constants, 6k resistance
# AUDIO ROUTING
w 30 0C 0E # HPL routing: Left channel's DAC reconstruction filter's positive terminal
w 30 0D 0E # HPR routing: Right channel's DAC reconstruction filter's positive terminal
w 30 0E 08 # LOL routing: Left channel's DAC reconstruction filter output
w 30 0F 08 # LOR routing: Right channel's DAC reconstruction filter output
w 30 34 40 # IN1L is routed to Left MICPGA with 10K resistance
w 30 36 40 # CM1L is routed to Left MICPGA via CM1L with 10K resistance
w 30 37 40 # IN1R is routed to Right MICPGA with 10K resistance
w 30 39 40 # CM1R is routed to Right MICPGA via CM1R with 10K resistance
# DC FILTER LEFT CHANNEL
w 30 00 08 # Select register page 8
w 30 18 7F # n0 + n1 * z^-1
w 30 19 FF # H(z) = ----------------------
w 30 1A 00 # 2^23 - d1 * z^-1
w 30 1C 80 #
w 30 1D 01 # The constants are defined as
w 30 1E 00 # n0 = 32767 * 256
w 30 20 7F # n1 = -32767 * 256
w 30 21 FC # d1 = 32768 * 256 * (1- 2^13)
w 30 22 00 # This gives a filter with cutoff at approx. 1 Hz
# DC FILTER RIGHT CHANNEL
w 30 00 09 # Select register page 9
w 30 20 7F # n0 + n1 * z^-1
w 30 21 FF # H(z) = ----------------------
w 30 22 00 # 2^23 - d1 * z^-1
w 30 24 80 #
w 30 25 01 # The constants are defined as
w 30 26 00 # n0 = 32767 * 256
w 30 28 7F # n1 = -32767 * 256
w 30 29 FC # d1 = 32768 * 256 * (1- 2^13)
w 30 2A 00 # This gives a filter with cutoff at approx. 1 Hz
#Inactive to low power
w 30 00 01 # Select register page 1
w 30 33 44 # Enable MICBIAS connected to AVDD
w 30 3B 80 # MicPGA Gain Control 0
w 30 3C 80 # MicPGA Gain Control 0
w 30 00 00 # Select register page 0
w 30 51 C0 # Power up ADC channels
#Low power to active
w 30 00 01 # Select register page 1
w 30 10 00 # HPL driver: Unmute, 0 dB gain
w 30 11 00 # HPR driver: Unmute, 0 dB gain
w 30 12 00 # LOL driver: Unmute, 0 dB gain
w 30 13 00 # LOR driver: Unmute, 0 dB gain
w 30 09 3F # All output drivers powered up
d 100
w 30 3B 3C # MicPGA Gain Control
w 30 3C 3C # MicPGA Gain Control
w 30 18 05 # Mixer Amplifier Control L
w 30 19 05 # Mixer Amplifier Control R
w 30 10 0a # HPL driver: 10 dB gain
w 30 11 0a # HPR driver: 10 dB gain
w 30 00 00 # Select register page 0
w 30 3F D6 # Power up the DAC channels, normal channel routing, soft-stepping disabled
#Active to low power
w 30 00 01 # Select register page 1
w 30 10 40 # HPL driver: Mute, 0 dB gain
w 30 11 40 # HPR driver: Mute, 0 dB gain
w 30 12 40 # LOL driver: Mute, 0 dB gain
w 30 13 40 # LOR driver: Mute, 0 dB gain
w 30 18 40 # Mixer Amplifier Control L:Mute
w 30 19 40 # Mixer Amplifier Control R:Mute
w 30 09 00 # All output drivers powered down
w 30 00 00 # Select register page 0
w 30 41 81 # Set minimum left DAC digital volume (-63.5 dB)
w 30 42 81 # Set minimum right DAC digital volume (-63.5 dB)
w 30 40 0C # Mute the DAC digital volume control
w 30 3F 16 # Power down the DAC channels, normal channel routing, soft-stepping disabled
#Low power to inactive
w 30 00 01 # Select register page 1
w 30 3B 80 # Set minimum left MICPGA gain
w 30 3C 80 # Set minimum right MICPGA gain
w 30 33 30 # Disable MICBIAS connected to AVDD
w 30 00 00 # Select register page 0
w 30 52 88 # Mute ADC channels
w 30 51 00 # Power down ADC channels
#SR-Switch to Off
# PIN RESET
p Reset 0 # Assert reset pin
我帮你把这个帖子贴到英文论坛了。你可以到这里去查看。
http://e2e.ti.com/support/low_power_rf/f/382/t/332174.aspx
感谢Nutcracker！
通过调整配置顺序，我已经解决了这个问题。
感谢Nutcracker！
通过调整配置顺序，我已经解决了这个问题。