allegro16.2导入网表的时候出现以下提示

请高手帮忙看一下，这个是什么原因，PCB工程师上次已经把原理图导入PCB了，并且已经布局了，我现在更新了原理图之后，自己再导入就出现下面的提示了。

Cadence Design Systems, Inc. netrev 16.2 Thu Sep 13 14:31:07 2012
(C) Copyright 2002 Cadence Design Systems, Inc.
------ Directives ------
RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'E:/PanXiaoya/CoM-9G45/CoM-9G45/PCB';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'E:/PanXiaoya/CoM-9G45/CoM-9G45/PCB/EAC9G45_BB-20120913A.brd';
NEW_BOARD_NAME 'E:/PanXiaoya/CoM-9G45/CoM-9G45/PCB/EAC9G45_BB-20120913A.brd';
CmdLine: netrev -$ -i E:/PanXiaoya/CoM-9G45/CoM-9G45/PCB -y 1 E:/PanXiaoya/CoM-9G45/CoM-9G45/PCB/#Ta02668.tmp
------ Preparing to read pst files ------

#1 ERROR(24) File not found
Packager files not found
#2 ERROR(102) Run stopped because errors were detected
netrev run on Sep 13 14:31:07 2012
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>？@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
2 errors detected
No oversight detected
No warning detected
cpu time 0:00:29
elapsed time 0:00:00