Ten Habits of Highly Successful Board Designers
时间：10-02
整理：3721RD
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By Eric Bogatin
Sometimes an OK answer NOW！ is better than a good answer late. Welcome to the real world of
deadlines and constraints. Of course, there is no substitute for modeling, simulating and
measuring design features, like via stub length, spacing between signal lines or coupling in a
differential pair. Design decisions should be based on sound analysis. However, not every
designer has the expertise, access to the tools, or the time to do the right analysis and they have
to make design decisions NOW！
If you are serious about high speed hardware design, whether it is chips, packages, circuit
boards, cables, connectors, or systems, it is important to use each design as an opportunity to
move farther up the learning curve so the next design is completed faster, cheaper, at lower risk
or higher performance. With each new design, always try to add a little bit more analysis in your
design process as an investment in your future.
When you are just starting out, and you don’t have time to spend a month reading textbooks,
taking classes and learning the best tools, you still have to get that board out by the end of the
day. “Do your own analysis” is not an acceptable answer. What are you to do?
I am asked this question all the time from designers and engineers I meet in my classes, at
conferences and at talks that I give. In response, I've created a few different “cheat sheets” for
signal integrity.
At the last PCB Design Conference at which I presented, a designer come up to me and said, “I
don’t know much about signal integrity, and I don’t get much chance to take classes. I can’t keep
150 design guidelines in my head. I just want 10 things I should watch for in my board design. If I
have to follow 10 design guidelines, what are the 10 things I should be doing?”
So, here is my answer. I call them “The 10 Habits of Highly Successful Board Designers.” If you
are not going to do your own analysis, and are only going to remember 10 things, here they are:
1. Design all interconnects as controlled impedance
Reduce reflection noise by keeping the instantaneous impedance the signal sees constant all
through its path, using a constant cross section trace and minimize discontinues along the way.
2. Space out signals as far as possible
This will reduce the cross talk, both near end and far end, between transmission lines in a bus.
How far is far enough? As a starting place, keep the spacing at least twice the line width.
3. Don’t cross the return current streams.
Not only does this paraphrase what Dr. Vintner said to his fellow Ghostbusters, it is also the
overall guideline to minimize ground bounce. Control the return paths as carefully as signal paths.
4. Do not allow signals to cross gaps in return planes.
See habit #3. Providing a continuous return current path will minimize ground bounce and prevent
your planes from turning into patch antennas and radiating.
5. Use return vias adjacent to EVERY signal via
See habit #3. Using return vias will minimize ground bounce and minimize noise injected into the
power and ground planes which contribute to long range cross talk and EMI.
6. Keep via stubs short
It’s the via stub that contributes to 95% of the signal integrity problems of vias. Keeping them
short will make vias nearly transparent to transmitted signal.
7. Use loosely coupled differential pairs, with symmetrical lines
If loss is important, you will have wider lines with loosely coupled pairs. Prevent differential
signals converting to common signals by keeping the two lines symmetrical.
8. Use multiple power and ground planes on adjacent layers with thin dielectric between
them
To minimize the voltage drop in the power distribution path, use low loop inductance
interconnects. Three design knobs affect loop inductance: short, wide, and power paths as close
as possible to their return.
9. Use shortest surface traces possible for decoupling capacitors.
See habit #8. Short, wide surface traces will minimize the loop inductance of decoupling
capacitors and minimize the peak, parallel resonances in the power distribution network.
10. If you don’t use SPICE to simulate the impedance profile of the decoupling capacitors;
per power/gnd pin pair, use 2 each of 1 uf, 0.1 uf, 0.01 uf and 0.001 uf, located in proximity
to device.
This is based on the assumption that there could be ¼ Amp peak current at any frequency per
power and ground pin pair, and with good engineering, you can achieve 2 nH of loop inductance
per capacitor. This habit is based on the SPICE simulation of the impedance profile.
Never follow a rule blindly, but it you are not going to do your own analysis, and you have to
make design decisions NOW！, these are really good habits which will give your next design a
better chance of being successful.
Sometimes an OK answer NOW！ is better than a good answer late. Welcome to the real world of
deadlines and constraints. Of course, there is no substitute for modeling, simulating and
measuring design features, like via stub length, spacing between signal lines or coupling in a
differential pair. Design decisions should be based on sound analysis. However, not every
designer has the expertise, access to the tools, or the time to do the right analysis and they have
to make design decisions NOW！
If you are serious about high speed hardware design, whether it is chips, packages, circuit
boards, cables, connectors, or systems, it is important to use each design as an opportunity to
move farther up the learning curve so the next design is completed faster, cheaper, at lower risk
or higher performance. With each new design, always try to add a little bit more analysis in your
design process as an investment in your future.
When you are just starting out, and you don’t have time to spend a month reading textbooks,
taking classes and learning the best tools, you still have to get that board out by the end of the
day. “Do your own analysis” is not an acceptable answer. What are you to do?
I am asked this question all the time from designers and engineers I meet in my classes, at
conferences and at talks that I give. In response, I've created a few different “cheat sheets” for
signal integrity.
At the last PCB Design Conference at which I presented, a designer come up to me and said, “I
don’t know much about signal integrity, and I don’t get much chance to take classes. I can’t keep
150 design guidelines in my head. I just want 10 things I should watch for in my board design. If I
have to follow 10 design guidelines, what are the 10 things I should be doing?”
So, here is my answer. I call them “The 10 Habits of Highly Successful Board Designers.” If you
are not going to do your own analysis, and are only going to remember 10 things, here they are:
1. Design all interconnects as controlled impedance
Reduce reflection noise by keeping the instantaneous impedance the signal sees constant all
through its path, using a constant cross section trace and minimize discontinues along the way.
2. Space out signals as far as possible
This will reduce the cross talk, both near end and far end, between transmission lines in a bus.
How far is far enough? As a starting place, keep the spacing at least twice the line width.
3. Don’t cross the return current streams.
Not only does this paraphrase what Dr. Vintner said to his fellow Ghostbusters, it is also the
overall guideline to minimize ground bounce. Control the return paths as carefully as signal paths.
4. Do not allow signals to cross gaps in return planes.
See habit #3. Providing a continuous return current path will minimize ground bounce and prevent
your planes from turning into patch antennas and radiating.
5. Use return vias adjacent to EVERY signal via
See habit #3. Using return vias will minimize ground bounce and minimize noise injected into the
power and ground planes which contribute to long range cross talk and EMI.
6. Keep via stubs short
It’s the via stub that contributes to 95% of the signal integrity problems of vias. Keeping them
short will make vias nearly transparent to transmitted signal.
7. Use loosely coupled differential pairs, with symmetrical lines
If loss is important, you will have wider lines with loosely coupled pairs. Prevent differential
signals converting to common signals by keeping the two lines symmetrical.
8. Use multiple power and ground planes on adjacent layers with thin dielectric between
them
To minimize the voltage drop in the power distribution path, use low loop inductance
interconnects. Three design knobs affect loop inductance: short, wide, and power paths as close
as possible to their return.
9. Use shortest surface traces possible for decoupling capacitors.
See habit #8. Short, wide surface traces will minimize the loop inductance of decoupling
capacitors and minimize the peak, parallel resonances in the power distribution network.
10. If you don’t use SPICE to simulate the impedance profile of the decoupling capacitors;
per power/gnd pin pair, use 2 each of 1 uf, 0.1 uf, 0.01 uf and 0.001 uf, located in proximity
to device.
This is based on the assumption that there could be ¼ Amp peak current at any frequency per
power and ground pin pair, and with good engineering, you can achieve 2 nH of loop inductance
per capacitor. This habit is based on the SPICE simulation of the impedance profile.
Never follow a rule blindly, but it you are not going to do your own analysis, and you have to
make design decisions NOW！, these are really good habits which will give your next design a
better chance of being successful.