北京没有PCB聚会或者是学习、培训？

以前搞过两次。

看看是否有需要来第三次，这得问amanda，不过神仙姐姐特别忙！呵呵

神仙姐姐考虑组织一下活动吧。

清华有一个将硬件设计的，你可以在21IC看到一些信息

惭愧惭愧啊，对不住大家！

现在的时间确实不象以前那样多了，恐难保证组织活动的精力和质量。

力荐开山鼻祖，夹湾沟小编出山主持！

辅助工作，我定全力而为。

请大家欢迎，踊跃发言！

听说29号有个CADANCE的培训！

哦，是CADANCE的技术交流会！

你想学什么?

我不建议你去CADANCE公司去培训，太贵！

明天去参加Cadence 2005年巡回技术研讨会，说不定能遇到老熟人，呵呵。

哪次不遇到老熟人呀！   

我申请了Cadence 2005年巡回技术研讨会，可能是时间太晚了没被批准，请你们去了的几位谈谈会上的大体内容或者感想好吗?遇到老熟人特开心吧！

Allegro 15.5的新特性

汗。

分成100K的文件都传不上来

一、Real Time DFA DRC

• New technology inside PCB Editor that offers real time component clearance analysis

• Spreadsheet driven rules table supporting Class instance level parameters

• Real time graphical feedback as component infringes on adjacent component

• Syntax support for Side to Side; End to End; Side to End Profile Checking

• Top/Bottom Side Parameters

二、Placement User Interface• New filtering options reduce component list to manageable state

• Component association hierarchy

– Requires Design Editor620 Front End

三、Testability Enhancements

• User Interface Redesign

• Expansion of Via Replacement Options (Top PCR)

• Probe Type Attributes (100,75, 50 Mil)

• Probe Density Checker

• Resequence TP names

• Analysis Report

四、Thieving

• Primarily used to balance copper on outer layers of PCB

• User controls for pad type, size, pitch and clearance to etch objects

五、Layer Set Routing and DRC

• New DRC to control routing by Layer Sets

• Layer Sets can contain 1 - N layers; assign to buses, nets, DPs

• Multiple Layer Sets can be assigned

• Typical use models – return path aware routing, shielding,impedance controlled routing

• Once a net begins on one layer of a set, it is then is locked to only associated layers

六、DRC Reporting in Constraint Manager

• New worksheet “DRC” organizes views and results for electrical,spacing, physical and design constraints

• Cross Probe to DRC location in PCB Editor

谢谢amanda！内容挺多的！

amanda JJ,我想进一步学习powerpcb5.0或pads2005,就是不知道北京哪儿有培训的?请告之！谢谢！