求救~！为什么我从逻辑图导入layout的时候,封装都过不去呢~~~

做完逻辑图,封装也都给定之后,我Tool---pads layout link---design----sendnetlist

然后在layout中,就只有电容的封装,其他的都说找不到封装

这是怎么回事啊,要怎么半啊~~~

这是错误报告的一部分,都差不多

Reading file --  F:\PADS Projects\padsnet.asc
No decals assigned for part type POWER_INPUT
Part name already used Q4
J1      OWER_INPUT@POWER_IN1">POWER_INPUT@POWER_IN1

No decals assigned for part type SW100
Part name already used Q4
J2      SW100@SIP3

No decals assigned for part type 7805
Part name already used Q4
U2      7805@TO226-3

No decals assigned for part type 7905
Part name already used Q4
U3      7905@TO-220

No decals assigned for part type SWA
Part name already used Q4
J3      SWA@SMA

No decals assigned for part type SWA
Part name already used Q4
J4      SWA@SMA

package没完整，在powerpcb，package包括decals and parts缺一不可。

请问,package是什么啊,不是只要画好逻辑图,给它一个pcb封装就可以的吗

谢谢~~

对于powerpcb tool而然package=元件pcb封装=decals and parts