求助：分频器的仿真图出不来

程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(clk:in std_logic;
clk1,clk0:out std_logic);
end fenpin;
architecture arch of fenpin is
signal clk_mid0,clk_mid:std_logic;
begin
process(clk)
variable data:integer range 0 to 25000;
begin
if clk'event and clk='1' then
if data=25000 then
data:=0;
clk_mid0<=not clk_mid0;
else
data:=data+1;
end if;
end if;
clk0<=clk_mid0;
end process;
process(clk)
variable data:integer range 0 to 625;
begin
if clk'event and clk='1'then
if data=625 then
data:=0;
clk_mid<=not clk_mid;
else
data:=data+1;
end if;
end if;
clk1<=clk_mid;
end process;
end arch;
我看书上写着，要接入一个50mhz的晶振电路，晶振电路的模块是怎么来的?具体怎么做呀?我不太懂

那肯定是你逻辑有问题

程序是抄书上的

你写激励信号了吗?50MHz的时钟是激励信号里面给出来的，没有激励信号怎么会出波形呢