仿真结果为啥步正确呢?
时间:10-02
整理:3721RD
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以下程序是关于有效数据之后插入冗余数据,输入输出均遵循AXI-strem协议,我一共插入了7个数据,为啥仿真的时候,插入的冗余数据就显示一个,不该是显示7个相同的数据吗?求各位大侠指点下,谢啦
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/04/26 16:33:58
// Design Name:
// Module Name: dummy_insert
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//端口声明
module dummy_insert(
clk,
rstn,
s_data_tvalid,
s_data_tdata,
s_data_tready,
s_data_tlast,
m_data_tvalid,
m_data_tdata,
m_data_tready,
m_data_tlast
);
parameter INSERT_NUM = 7;
parameter DUMMY_DATA = 4'b1001;
//input and output
input clk;
input rstn;
input s_data_tvalid;
input[3:0] s_data_tdata;
output s_data_tready;
input s_data_tlast;
output m_data_tvalid;
output[3:0] m_data_tdata;
input m_data_tready;
output m_data_tlast;
//插入冗余数据选择标志信号
reg dummy_sel;
always @(posedge clk)
begin
if(rstn == 1'b0) begin
dummy_sel <= 1'b0;
end
else if(s_data_tlast) begin
dummy_sel <= 1'b1;
end
else if(m_data_tlast) begin
dummy_sel <= 1'b0;
end
end
//m_data_tvalid(整个传输时间)
reg m_data_tvalid_t;
reg m_data_tvalid_insert;
wire m_data_tvalid;
//有效数据传输
always @(posedge clk)
begin
if(rstn == 1'b0) begin
m_data_tvalid_t <= 1'b0;
end
else begin
m_data_tvalid_t <= s_data_tvalid;
end
end
//冗余数据传输
always @(posedge clk)
begin
if(rstn == 1'b0) begin
m_data_tvalid_insert <= 1'b0;
end
else begin
m_data_tvalid_insert <= dummy_sel & m_data_tready & s_data_tvalid;
end
end
assign m_data_tvalid = m_data_tvalid_t | m_data_tvalid_insert;
//m_data_tlast
reg [2:0] cnt_dummy;
always @(posedge clk)
begin
if(rstn==1'b0 || s_data_tlast == 1'b1) begin
cnt_dummy <= 2'd0;
end
else if(cnt_dummy < INSERT_NUM && dummy_sel && m_data_tready ) begin
cnt_dummy <= cnt_dummy + 1'b1;
end
end
assign m_data_tlast = (cnt_dummy == INSERT_NUM-1) & m_data_tready;
//m_data_tdata
reg [3:0] m_data_tdata_t;
always @(posedge clk)
begin
if(s_data_tvalid & s_data_tready) begin//有效数据传输
m_data_tdata_t <= s_data_tdata;
end
else if(m_data_tvalid_insert) begin
m_data_tdata_t <= DUMMY_DATA;//冗余数据传输
end
end
assign m_data_tdata = m_data_tdata_t;
//s_data_tready
assign s_data_tready = (~dummy_sel) & m_data_tready;//传有效数据时 为高电平
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/04/26 16:33:58
// Design Name:
// Module Name: dummy_insert
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//端口声明
module dummy_insert(
clk,
rstn,
s_data_tvalid,
s_data_tdata,
s_data_tready,
s_data_tlast,
m_data_tvalid,
m_data_tdata,
m_data_tready,
m_data_tlast
);
parameter INSERT_NUM = 7;
parameter DUMMY_DATA = 4'b1001;
//input and output
input clk;
input rstn;
input s_data_tvalid;
input[3:0] s_data_tdata;
output s_data_tready;
input s_data_tlast;
output m_data_tvalid;
output[3:0] m_data_tdata;
input m_data_tready;
output m_data_tlast;
//插入冗余数据选择标志信号
reg dummy_sel;
always @(posedge clk)
begin
if(rstn == 1'b0) begin
dummy_sel <= 1'b0;
end
else if(s_data_tlast) begin
dummy_sel <= 1'b1;
end
else if(m_data_tlast) begin
dummy_sel <= 1'b0;
end
end
//m_data_tvalid(整个传输时间)
reg m_data_tvalid_t;
reg m_data_tvalid_insert;
wire m_data_tvalid;
//有效数据传输
always @(posedge clk)
begin
if(rstn == 1'b0) begin
m_data_tvalid_t <= 1'b0;
end
else begin
m_data_tvalid_t <= s_data_tvalid;
end
end
//冗余数据传输
always @(posedge clk)
begin
if(rstn == 1'b0) begin
m_data_tvalid_insert <= 1'b0;
end
else begin
m_data_tvalid_insert <= dummy_sel & m_data_tready & s_data_tvalid;
end
end
assign m_data_tvalid = m_data_tvalid_t | m_data_tvalid_insert;
//m_data_tlast
reg [2:0] cnt_dummy;
always @(posedge clk)
begin
if(rstn==1'b0 || s_data_tlast == 1'b1) begin
cnt_dummy <= 2'd0;
end
else if(cnt_dummy < INSERT_NUM && dummy_sel && m_data_tready ) begin
cnt_dummy <= cnt_dummy + 1'b1;
end
end
assign m_data_tlast = (cnt_dummy == INSERT_NUM-1) & m_data_tready;
//m_data_tdata
reg [3:0] m_data_tdata_t;
always @(posedge clk)
begin
if(s_data_tvalid & s_data_tready) begin//有效数据传输
m_data_tdata_t <= s_data_tdata;
end
else if(m_data_tvalid_insert) begin
m_data_tdata_t <= DUMMY_DATA;//冗余数据传输
end
end
assign m_data_tdata = m_data_tdata_t;
//s_data_tready
assign s_data_tready = (~dummy_sel) & m_data_tready;//传有效数据时 为高电平
endmodule
插入的数据是9吗?你这里有6个啊,你要看这个数据占了几个时钟,相同的数据当然就只显示一次了,但是显示一次不代表我只有一个数据,要看时钟个数!
上面截图不全 这是全图
这是Verlog HDL吗?
对呀 ,程序我看着没问题呀 ,但是仿真结果跟我预想的有区别呀,虽然插入了冗余数据,但是我想插7个,它只显示了一个,求大侠解答
之前的我搞清楚了,谢谢你。我想请教一下,就是我想插入10个数据,为什么每次插入都是少一个呢,是不是跟时延有关系
你要插入几个这是通过计数器来走的啊,你要有个专门的计数器,那不就是想要几个就有几个吗
刚开始看了下Verlog HDL,准备面试~
刚看了 就准备面试。大神呀 但是感觉这个方向待遇没有互联网好啊
为了面试准备的。并没有要玩Verlog HDL 的想法。