PLL的N分频参数控制模块 求N值的确定问题
时间:10-02
整理:3721RD
点击:
N分频参数控制模块:
module PLL_counter_N (clk,fin,rst,count_N);
input fin;//???à?·ê?è?D?o?
input clk;//?μí3ê±?ó
input rst;
output count_N;
reg [14:0]count_N;
reg [15:0]cnt;
reg cnt_en;
reg load;
wire cnt_clr;
always@(posedge fin)//finé?éy??μ?à′ê±£?2úéú?÷??????±ê??
begin
if(!rst)
begin
cnt_en=0;
load=1;
end
else
begin
cnt_en=~cnt_en;
load=~cnt_en;
end
end
assign cnt_clr=~(~fin&load);
always@(posedge clk or negedge cnt_clr)
begin
if(!cnt_clr)
begin cnt<=0;end
else if(cnt==65536)
begin cnt<=0;end
else
begin cnt<=cnt+1;end
end
always@(posedge fin)
begin
count_N<=cnt/2;
end
endmodule
Testbench模块:
module counter_N_tb;
reg fin,clk,rst;
wire [14:0]count_N;
PLL_counter_N counterN(.fin(fin),.clk(clk),.rst(rst),.count_N(count_N));
always
begin
#1 clk<=~clk;
end
always
begin
#100 fin<=~fin;
end
initial
begin
rst<=1;
clk<=1;
fin<=1;
#100 rst<=0;
#200 rst<=1;
#100 rst<=0;
#50 rst<=1;
end
endmodule
求解答,波形仿真count_N的值为什么是这样?求改进方法。
module PLL_counter_N (clk,fin,rst,count_N);
input fin;//???à?·ê?è?D?o?
input clk;//?μí3ê±?ó
input rst;
output count_N;
reg [14:0]count_N;
reg [15:0]cnt;
reg cnt_en;
reg load;
wire cnt_clr;
always@(posedge fin)//finé?éy??μ?à′ê±£?2úéú?÷??????±ê??
begin
if(!rst)
begin
cnt_en=0;
load=1;
end
else
begin
cnt_en=~cnt_en;
load=~cnt_en;
end
end
assign cnt_clr=~(~fin&load);
always@(posedge clk or negedge cnt_clr)
begin
if(!cnt_clr)
begin cnt<=0;end
else if(cnt==65536)
begin cnt<=0;end
else
begin cnt<=cnt+1;end
end
always@(posedge fin)
begin
count_N<=cnt/2;
end
endmodule
Testbench模块:
module counter_N_tb;
reg fin,clk,rst;
wire [14:0]count_N;
PLL_counter_N counterN(.fin(fin),.clk(clk),.rst(rst),.count_N(count_N));
always
begin
#1 clk<=~clk;
end
always
begin
#100 fin<=~fin;
end
initial
begin
rst<=1;
clk<=1;
fin<=1;
#100 rst<=0;
#200 rst<=1;
#100 rst<=0;
#50 rst<=1;
end
endmodule
求解答,波形仿真count_N的值为什么是这样?求改进方法。
支持一下,感谢分享~~~~~