编译出现产生了latch的warning，求解决办法

时间：10-02 整理：3721RD 点击：

module test21(Iavg_EOC,CLK,RSTn,Iavg,end_frequency,current_frequency,start);
input CLK;
input RSTn;
input Iavg_EOC;
input [11:0]Iavg;
output [13:0]end_frequency;
output [13:0]current_frequency;
output start;
reg [13:0]end_frequency;
reg [13:0]current_frequency;
reg start;
reg [11:0]I_Value1;
reg [11:0]I_Value0;
reg i;
always @(posedge CLK or negedge RSTn)
if(！RSTn)
begin
current_frequency I_Value0)
                  begin
                     current_frequency<=current_frequency+14'd10;
                     end_frequency<=end_frequency+14'd10;
                     I_Value0<=I_Value1;
                     i<=1'b1;
                  end
               else if(I_Value1<I_Value0)
                  begin
                     current_frequency<=current_frequency+14'd10;
                     end_frequency<=end_frequency;
                     i<=1'b1;
                  end
               else
                  begin
                     current_frequency<=current_frequency+14'd10;
                     end_frequency<=end_frequency;
                  end
            end
            else
            begin
               current_frequency<=current_frequency;
               end_frequency<=end_frequency;
            end
         end
   end
   else
   begin
   current_frequency<=current_frequency;
      end_frequency<=end_frequency;
      start<=1'b1;
   end
end
endmodule

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