modelsim仿真是出现warning，不去波形，求解答

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst9
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst9
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst9
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst8
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst8
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst8
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst8
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst8
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
#    Time: 0 ps  Iteration: 0  Instance: /svpwm_2_vhd_tst/i1/b2v_inst8

网上查到说是信号没有赋初值，可是我已经明明赋了，而且我测试文件也编写输入了。
它警告都是说8,9模块，是我8,9模块错了吗?
================第八模块===========================
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vector_time is
Port(Ts: in INTEGER;
     Ud: in INTEGER;
     Uab: in std_logic_vector(7 downto 0);
     Ubc: in std_logic_vector(7 downto 0);
     Uca: in std_logic_vector(7 downto 0);
     N:in INTEGER;
     Tx: out INTEGER;
     Ty: out INTEGER);
end vector_time;
architecture Behavioral of vector_time is
signal x, y : INTEGER:=0;
begin
process(Uab,Ubc,Uca,N)
variable temp_1:integer range 0 to 255;
variable temp_2:integer range 0 to 255;
variable temp_3:integer range 0 to 255;
begin
temp_1 := conv_integer(Uab);
temp_2 := conv_integer(Ubc);
temp_3 := conv_integer(Uca);
case N is
when 1=>x x x x x x null;
end case;
end process;
Tx =0 else'0';
x(1) =0 else'0';
x(0) =0 else'0';
process(x)
begin
case x is
when"110"=>N N N N N N null;
end case;
end process;
end Behavioral;
求大神解答

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