SPI总线的VHDL设计
时间:10-02
整理:3721RD
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求帮忙!波形仿真library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is --
port( sclk:in std_logic;
cs:in std_logic;
read:in std_logic;
write:in std_logic;
din:in std_logic;
dout:out std_logic;
rec_int:out std_logic;
data_out:out std_logic_vector(15 downto 0);
data_in:in std_logic_vector(15 downto 0));
end spi;
architecture exe of spi is
signal txhold:std_logic_vector(15 downto 0);
signal rxhold:std_logic_vector(15 downto 0);
signal txshift:std_logic_vector(15 downto 0);
signal rxshift:std_logic_vector(15 downto 0);
signal doutbit:std_logic;
signal txcnt:std_logic_vector(4 downto 0);
signal rxcnt:std_logic_vector(4 downto 0);
begin
send_data:
process(write)
begin
if write'event and write='0'then
txhold 'Z');
--txhold<=data_in when write='0' else txhold;
txshift_pro:
process(cs,sclk)
begin
if cs='1' then
txcnt<="00000";
txshift<=txhold;
dout<='0';
elsif sclk'event and sclk='1' then
if txcnt="01111" then
dout<=txshift(15);
txcnt<="10000";
elsif txcnt="10000" then
txcnt<="10000";
else
dout<=txshift(15);
txshift<=txshift(14 downto 0)&'0';
txcnt<=txcnt+"00001";
end if;
end if;
end process;
rxshift_pro:
process(cs,sclk)
begin
if cs='1' then
rxcnt<="00000";
rxhold<=rxshift;
rec_int<='1';
elsif sclk'event and sclk='1' then
if txcnt="01111" then
rxshift(15 downto 0)<=rxshift(14 downto 0)&din;
rxcnt<="10000";
rec_int<='0';
elsif rxcnt="10000" then
rxcnt<="10000";
rec_int<='1';
else
rxshift<=rxshift(14 downto 0)&din;
rxcnt<=rxcnt+"00001";
end if;
end if;
end process;
end exe;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is --
port( sclk:in std_logic;
cs:in std_logic;
read:in std_logic;
write:in std_logic;
din:in std_logic;
dout:out std_logic;
rec_int:out std_logic;
data_out:out std_logic_vector(15 downto 0);
data_in:in std_logic_vector(15 downto 0));
end spi;
architecture exe of spi is
signal txhold:std_logic_vector(15 downto 0);
signal rxhold:std_logic_vector(15 downto 0);
signal txshift:std_logic_vector(15 downto 0);
signal rxshift:std_logic_vector(15 downto 0);
signal doutbit:std_logic;
signal txcnt:std_logic_vector(4 downto 0);
signal rxcnt:std_logic_vector(4 downto 0);
begin
send_data:
process(write)
begin
if write'event and write='0'then
txhold 'Z');
--txhold<=data_in when write='0' else txhold;
txshift_pro:
process(cs,sclk)
begin
if cs='1' then
txcnt<="00000";
txshift<=txhold;
dout<='0';
elsif sclk'event and sclk='1' then
if txcnt="01111" then
dout<=txshift(15);
txcnt<="10000";
elsif txcnt="10000" then
txcnt<="10000";
else
dout<=txshift(15);
txshift<=txshift(14 downto 0)&'0';
txcnt<=txcnt+"00001";
end if;
end if;
end process;
rxshift_pro:
process(cs,sclk)
begin
if cs='1' then
rxcnt<="00000";
rxhold<=rxshift;
rec_int<='1';
elsif sclk'event and sclk='1' then
if txcnt="01111" then
rxshift(15 downto 0)<=rxshift(14 downto 0)&din;
rxcnt<="10000";
rec_int<='0';
elsif rxcnt="10000" then
rxcnt<="10000";
rec_int<='1';
else
rxshift<=rxshift(14 downto 0)&din;
rxcnt<=rxcnt+"00001";
end if;
end if;
end process;
end exe;
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