微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 嵌入式设计讨论 > FPGA,CPLD和ASIC > 求解决:全编译都通过,但用singletap编译不通过

求解决:全编译都通过,但用singletap编译不通过

时间:10-02 整理:3721RD 点击:
Error: Found I/O cells that do not connect to top-level pins or have illegal connectivity
        Error: Output I/O cell "pre_syn.bp.data_0_~output" in partition "Top" driving " "
        Error: Output I/O cell "pre_syn.bp.data_1_~output" in partition "Top" driving " "
        Error: Output I/O cell "pre_syn.bp.data_2_~output" in partition "Top" driving " "
        Error: Output I/O cell "pre_syn.bp.data_3_~output" in partition "Top" driving " "
        Error: Output I/O cell "pre_syn.bp.data_4_~output" in partition "Top" driving " "
        Error: Output I/O cell "pre_syn.bp.data_5_~output" in partition "Top" driving " "
        Error: Output I/O cell "pre_syn.bp.data_6_~output" in partition "Top" driving " "
        Error: Output I/O cell "pre_syn.bp.data_7_~output" in partition "Top" driving " "
分析综合,全编译都通过,但用singletap编译不通过,请问这是怎么回事?



应该是你的IO口设置问题,仔细查查吧。

看看是不是引脚配置出现问题 CLK引脚地址分配错误

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top