请问我的Quartus在编译后自动调用ModelSim 就会仿真失败

求助：请问我的Quartus在编译后自动调用ModelSim 就会仿真失败
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./ripple_carry_counter_run_msim_gate_verilog.do PAUSED at line 20
，但是手动去点EDA RTL Simulation就可以仿真呢……

这是一个bug,,屏蔽do文件的对应行，再执行do文件就可以了

不好意思，请教一下怎么屏蔽这个do文件的对应行?

我在调用Modelsim的时候会出现这几个错误：
** Error: (vsim-SDF-3250) ab2pulse_vhd.sdo(0): Failed to find INSTANCE '/NA'.
#
# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).
#
# ** Error: (vsim-SDF-3250) ab2pulse_vhd.sdo(0): Failed to find INSTANCE '/NA'.

我在调用Modelsim的时候会出现这几个错误：
** Error: (vsim-SDF-3250) ab2pulse_vhd.sdo(0): Failed to find INSTANCE '/NA'.
#
# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).
#
# ** Error: (vsim-SDF-3250) ab2pulse_vhd.sdo(0): Failed to find INSTANCE '/NA'.