+两张图，看清时钟

一直在看例程 ，但现例程中没有时钟的配置程序，一开始也没有在意，现在把例程都试差不多了，反回来想想，有点费解。
由于没有看视频，今天发现视频里有一节是讲时钟的，就下载下来看成了一下。还是挻详细的。
原来时钟的配置在gel文件中。
根据视频的讲解，做了下面两张图，算是把时钟部分的要点总结一下，再深入就是研究DSP的了，而我们这些只是会用就行了。
以下是两个时钟PLL0与PLL1的产生。

下面是两个时钟的一些参数。

之于时钟的配置可以在gel文件中的device_PLL0与device_PLL1两个函数中。

1. device_PLL0(unsigned int CLKMODE, unsigned int PLLM, unsigned int POSTdiv,unsigned int PLLdiv1, unsigned int PLLdiv2, unsigned int PLLdiv3, unsigned int PLLdiv7 ) {
   
2. 
   
3.     unsigned int i=0;
   
4. 
   
5.     /* Clear PLL lock bit */
   
6.     CFGCHIP0 &= ~(0x00000010);
   
7. 
   
8.     /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
   
9.     PLL0_PLLCTL &= ~(0x00000020);
   
10. 
    
11.     /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
    
12.     PLL0_PLLCTL &= ~(0x00000200);
    
13. 
    
14.     /* Set PLLEN=0 to put in bypass mode*/
    
15.     PLL0_PLLCTL &= ~(0x00000001);
    
16. 
    
17.     /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
    
18.     for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}
    
19. 
    
20.     /* Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
    
21.     PLL0_PLLCTL &= 0xFFFFFEFF;
    
22.     PLL0_PLLCTL |= (CLKMODE << 8);
    
23. 
    
24.     /*Clear PLLRST bit to reset the PLL */
    
25.     PLL0_PLLCTL &= ~(0x00000008);
    
26. 
    
27.     /* Disable the PLL output*/
    
28.     PLL0_PLLCTL |= (0x00000010);
    
29. 
    
30.     /* PLL initialization sequence
    
31.     Power up the PLL by setting PWRDN bit set to 0 */
    
32.     PLL0_PLLCTL &= ~(0x00000002);
    
33. 
    
34.     /* Enable the PLL output*/
    
35.     PLL0_PLLCTL &= ~(0x00000010);
    
36. 
    
37.     /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
    
38.     for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}
    
39. 
    
40.     /*Program the required multiplier value in PLLM*/
    
41.     PLL0_PLLM    = PLLM;
    
42. 
    
43.     /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTdiv ratio*/
    
44.     PLL0_POSTdiv = 0x8000 | POSTdiv;
    
45. 
    
46.     /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
    
47.     while(PLL0_PLLSTAT & 0x1==1){}
    
48. 
    
49.     /*Program the RATIO field in PLLdivx with the desired divide factors. In addition, make sure in this step you leave the PLLdivx.DxEN bits set so clocks are still enabled (default).*/
    
50.     PLL0_PLLdiv1 = 0x8000 | PLLdiv1;             // Fixed Ratio /1
    
51.     PLL0_PLLdiv2 = 0x8000 | PLLdiv2;             // Fixed Ratio /2
    
52.     PLL0_PLLdiv4 = 0x8000 | (((PLLdiv1+1)*4)-1); // Fixed Ratio /4
    
53.     PLL0_PLLdiv6 = 0x8000 | PLLdiv1;             // Fixed Ratio /1
    
54.     PLL0_PLLdiv3 = 0x8000 | PLLdiv3;             // Variable Ratio (EMIF)
    
55.     PLL0_PLLdiv7 = 0x8000 | PLLdiv7;             // Variable Ratio (RMII)
    
56. 
    
57. 
    
58.     /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
    
59.     PLL0_PLLCMD |= 0x1;
    
60. 
    
61.     /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
    
62.     while(PLL0_PLLSTAT & 0x1==1) { }
    
63. 
    
64.     /*Wait for PLL to reset properly.*/
    
65.     for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}
    
66. 
    
67.     /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
    
68.     PLL0_PLLCTL |= 0x8;
    
69. 
    
70.     /*Wait for PLL to lock.*/
    
71.     for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;}
    
72. 
    
73.     /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
    
74.     PLL0_PLLCTL |=  0x1;
    
75. }
    
76. 
    
77. /**********************************************************************************
    
78. DDR PLL1 init:
    
79. 
    
80. ***********************************************************************************/
    
81. device_PLL1(unsigned int PLLM,unsigned int POSTdiv,unsigned int PLLdiv1, unsigned int PLLdiv2, unsigned int PLLdiv3 ) {
    
82. 
    
83.     unsigned int i=0;
    
84. 
    
85.     /* Clear PLL lock bit */
    
86.     CFGCHIP3 &= ~(0x00000020);
    
87. 
    
88.     /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
    
89.     PLL1_PLLCTL &= ~(0x00000020);
    
90. 
    
91.     /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
    
92.     PLL1_PLLCTL &= ~(0x00000200);
    
93. 
    
94.     /* Set PLLEN=0 to put in bypass mode*/
    
95.     PLL1_PLLCTL &= ~(0x00000001);
    
96. 
    
97.     /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
    
98.     for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}
    
99. 
    
100.     /*Clear PLLRST bit to reset the PLL */
     
101.     PLL1_PLLCTL &= ~(0x00000008);
     
102. 
     
103.     /* Disable the PLL output*/
     
104.     PLL1_PLLCTL |= (0x00000010);
     
105. 
     
106.     /* PLL initialization sequence
     
107.     Power up the PLL by setting PWRDN bit set to 0 */
     
108.     PLL1_PLLCTL &= ~(0x00000002);
     
109. 
     
110.     /* Enable the PLL output*/
     
111.     PLL1_PLLCTL &= ~(0x00000010);
     
112. 
     
113.     /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
     
114.     for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}
     
115. 
     
116.     /*Program the required multiplier value in PLLM*/
     
117.     PLL1_PLLM    = PLLM;
     
118. 
     
119.     /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTdiv ratio*/
     
120.     PLL1_POSTdiv = 0x8000 | POSTdiv;
     
121. 
     
122.     /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
     
123.     while(PLL1_PLLSTAT & 0x1==1){}
     
124. 
     
125.     /*Program the RATIO field in PLLdivx with the desired divide factors. In addition, make sure in this step you leave the PLLdivx.DxEN bits set so clocks are still enabled (default).*/
     
126.     PLL1_PLLdiv1 = 0x8000 | PLLdiv1;   // DDR frequency (aka 2X_CLK)
     
127.     PLL1_PLLdiv2 = 0x8000 | PLLdiv2;   // Optional CFGCHIP3[ASYNC3_CLKSRC] clock source
     
128.     PLL1_PLLdiv3 = 0x8000 | PLLdiv3;   // Optional PLL0 clock source
     
129. 
     
130.     /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
     
131.     PLL1_PLLCMD |= 0x1;
     
132. 
     
133.     /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
     
134.     while(PLL1_PLLSTAT & 0x1==1) { }
     
135. 
     
136.     /*Wait for PLL to reset properly */
     
137.     for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}
     
138. 
     
139.     /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
     
140.     PLL1_PLLCTL |= 0x8;
     
141. 
     
142.     /*Wait for PLL to lock. See PLL spec for PLL lock time*/
     
143.     for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;}
     
144. 
     
145.     /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
     
146.     PLL1_PLLCTL |=  0x1;
     
147. }

复制代码

其实gel文件中所做的工作还是很多的。之前用28335的时候没怎么在意gel文件，所有的配置都是在C程序中的，看来有必要学习一下gel文件了。