一些后端方面的问题（共105题）
时间：10-02
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从国外一个网站上看到的一些问题，有些比较基础，有的可能以前出现过，但面试、工作时可能会碰到，发上来大家讨论一下！
Q1. Explain the flow of physical design and inputs and outputs for each step in flow.
Q2. Why higher metal layers are preferred for Vdd and Vss?
Q3. Why clock is not synthesized in DC?
Q4. Which layer is used for clock routing and why?
Q5. Which is more complicated when you have a 32 MHz and 512 MHz clock design?
Q6. Whether congestion is related to placement or routing?
Q7. What parameters (or aspects) differentiate Chip Design & Block level design?
Q8. What is wire load model?
Q9. What is transition? What if transition time is more?
Q10. What is track assignment?
Q11. What is tie-high and tie-low cells and where it is used
Q12. What is threshold voltage? How it affect timing?
Q13. What is the significance of negative slack?
Q14. What is the difference between synthesis and simulation?
Q15. What is the difference between core filler cells and metal fillers?
Q16. What is signal integrity? How it affects Timing?
Q17. What is SDC constraint file contains?
Q18. What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
Q19. What is partial floor plan?
Q20. What is OPC, PSM?
Q21. What is negative slack ? How it affects timing?
Q22. What is metal density, metal slotting rule?
Q23. What is meant my 9 track, 12 track standard cells?
Q24. What corner cells contains?
Q25. What are types of routing?
Q26. What are the steps that you have done in the design flow?
Q27. What are the steps involved in designing an optimal pad ring?
Q28. What are the problems faced related to timing?
Q29. What are the common issues in floor plan?
Q30. What is logic optimization and give some methods of logic optimization.
Q31. What is LEF?
Q32. What is latency? Give the various latency types?
Q33. What is IR drop? How to avoid .how it affects timing?
Q34. What is hold problem? How can you avoid it?
Q35. What is grided and gridless routing?
Q36. What is floor plan and power plan?
Q37. What is ESD?
Q38. What is EM and it’s effect?
Q39. What is effective utilization and chip utilization?
Q40. What is each macro size and no. of standard cell count?
Q41. What is difference between normal buffer and clock buffer?
Q42. What is difference between HFN synthesis and CTS?
Q43. What is DEF?
Q44. What is cross talk? How can you avoid?
Q45. What is core and how you will decide w/h ratio for core?
Q46. What is content of lib, lef, sdc?
Q47. What is congestion?
Q48. What is cloning and buffering?
Q49. What is cell delay and net delay?
Q50. What is antenna effect? How it can be avoided?
Q51. What is a macro and standard cell?
Q52. What is a grid? Why we need different types of grids?
Q53. What is .lib, LEF, DEF, .tf?
Q54. What if hot spot found in some area of block? How you tackle this?
Q55. What are the Input needs for your design?
Q56. What are the input files will you give for primetime correlation?
Q57. What are the algorithms used while routing? Will it optimize wire length?
Q58. What are placement blockages?
Q59. What are high-Vt and low-Vt cells?
Q60. What are the common DFM issues?
Q61. What are delay models and what is the difference between them?
Q62. What are clock trees?
Q63. What are clock tree types?
Q64. Name few tools which you used for physical verification?
Q65. In your project what is die size, number of metal layers, technology, foundry, number of clocks?
Q66. In which layer do you prefer for clock routing and why?
Q67. If the routing congestion exists between two macros, then what will you do?
Q68. If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
Q69. If in your design has reset pin, then it’ll affect input pin or output pin or both?
Q70. How will you place the macros?
Q71. How will you decide the Pin location in block level design?
Q72. How will you decide the die size?
Q73. How to find total chip power?
Q74. How to find number of power pad and IO power pads?
Q75. How to decide number of pads in chip level design?
Q76. How to calculate core ring width, macro ring width and strap or trunk width?
Q77. How to calculate core ring and stripe widths?
Q78. How the width of metal and number of straps calculated for power and ground?
Q79. How slow and fast transition at inputs effect timing for gates?
Q80. How R and C values are affecting time?
Q81. How ohm (R), farad (C) is related to second (T)?
Q82. How much aspect ratio should be kept (or have you kept) and what is theutilization?
Q83. How many macros in your previous design?
Q84. How double spacing will avoid cross talk?
Q85. How do you place macros in a full chip design?
Q86. How did you do power planning?
Q87. How do you resolve the setup and hold time violation problem?
Q88. How did you handle the Clock in your design?
Q89. How delays vary with different PVT conditions? Show the graph.
Q90. How can you estimate area of block?
Q91. During power analysis, if you are facing IR drop problem, then how did you avoid?
Q92. Differentiate between a Hierarchical Design and flat design?
Q93. Define antenna problem and how did you resolve these problem?
Q94. After adding stripes also if you have hot spot, what do you do?
Q95. What is meant by scaling in VLSI design? Describe various effects of scaling.
Q96. What is meant by 90nm technology?
Q97. What is a transmission gate, and what is its typical use in VLSI?
Q98. What is ASIP?
Q99. What are the differences between gate array ASIC and cell based ASIC?
Q100. When you want the production in bulk amount which design style you prefer? Justify?
Q101. State the importance of Lithography in VLSI design?
Q102. Power Optimization Techniques for deep sub micron?
Q103. Define congestion in routing?
Q104. What do you mean by rip-up and re-routing?
Q105. What is Yield in fabrication process?
Q1. Explain the flow of physical design and inputs and outputs for each step in flow.
Q2. Why higher metal layers are preferred for Vdd and Vss?
Q3. Why clock is not synthesized in DC?
Q4. Which layer is used for clock routing and why?
Q5. Which is more complicated when you have a 32 MHz and 512 MHz clock design?
Q6. Whether congestion is related to placement or routing?
Q7. What parameters (or aspects) differentiate Chip Design & Block level design?
Q8. What is wire load model?
Q9. What is transition? What if transition time is more?
Q10. What is track assignment?
Q11. What is tie-high and tie-low cells and where it is used
Q12. What is threshold voltage? How it affect timing?
Q13. What is the significance of negative slack?
Q14. What is the difference between synthesis and simulation?
Q15. What is the difference between core filler cells and metal fillers?
Q16. What is signal integrity? How it affects Timing?
Q17. What is SDC constraint file contains?
Q18. What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
Q19. What is partial floor plan?
Q20. What is OPC, PSM?
Q21. What is negative slack ? How it affects timing?
Q22. What is metal density, metal slotting rule?
Q23. What is meant my 9 track, 12 track standard cells?
Q24. What corner cells contains?
Q25. What are types of routing?
Q26. What are the steps that you have done in the design flow?
Q27. What are the steps involved in designing an optimal pad ring?
Q28. What are the problems faced related to timing?
Q29. What are the common issues in floor plan?
Q30. What is logic optimization and give some methods of logic optimization.
Q31. What is LEF?
Q32. What is latency? Give the various latency types?
Q33. What is IR drop? How to avoid .how it affects timing?
Q34. What is hold problem? How can you avoid it?
Q35. What is grided and gridless routing?
Q36. What is floor plan and power plan?
Q37. What is ESD?
Q38. What is EM and it’s effect?
Q39. What is effective utilization and chip utilization?
Q40. What is each macro size and no. of standard cell count?
Q41. What is difference between normal buffer and clock buffer?
Q42. What is difference between HFN synthesis and CTS?
Q43. What is DEF?
Q44. What is cross talk? How can you avoid?
Q45. What is core and how you will decide w/h ratio for core?
Q46. What is content of lib, lef, sdc?
Q47. What is congestion?
Q48. What is cloning and buffering?
Q49. What is cell delay and net delay?
Q50. What is antenna effect? How it can be avoided?
Q51. What is a macro and standard cell?
Q52. What is a grid? Why we need different types of grids?
Q53. What is .lib, LEF, DEF, .tf?
Q54. What if hot spot found in some area of block? How you tackle this?
Q55. What are the Input needs for your design?
Q56. What are the input files will you give for primetime correlation?
Q57. What are the algorithms used while routing? Will it optimize wire length?
Q58. What are placement blockages?
Q59. What are high-Vt and low-Vt cells?
Q60. What are the common DFM issues?
Q61. What are delay models and what is the difference between them?
Q62. What are clock trees?
Q63. What are clock tree types?
Q64. Name few tools which you used for physical verification?
Q65. In your project what is die size, number of metal layers, technology, foundry, number of clocks?
Q66. In which layer do you prefer for clock routing and why?
Q67. If the routing congestion exists between two macros, then what will you do?
Q68. If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
Q69. If in your design has reset pin, then it’ll affect input pin or output pin or both?
Q70. How will you place the macros?
Q71. How will you decide the Pin location in block level design?
Q72. How will you decide the die size?
Q73. How to find total chip power?
Q74. How to find number of power pad and IO power pads?
Q75. How to decide number of pads in chip level design?
Q76. How to calculate core ring width, macro ring width and strap or trunk width?
Q77. How to calculate core ring and stripe widths?
Q78. How the width of metal and number of straps calculated for power and ground?
Q79. How slow and fast transition at inputs effect timing for gates?
Q80. How R and C values are affecting time?
Q81. How ohm (R), farad (C) is related to second (T)?
Q82. How much aspect ratio should be kept (or have you kept) and what is theutilization?
Q83. How many macros in your previous design?
Q84. How double spacing will avoid cross talk?
Q85. How do you place macros in a full chip design?
Q86. How did you do power planning?
Q87. How do you resolve the setup and hold time violation problem?
Q88. How did you handle the Clock in your design?
Q89. How delays vary with different PVT conditions? Show the graph.
Q90. How can you estimate area of block?
Q91. During power analysis, if you are facing IR drop problem, then how did you avoid?
Q92. Differentiate between a Hierarchical Design and flat design?
Q93. Define antenna problem and how did you resolve these problem?
Q94. After adding stripes also if you have hot spot, what do you do?
Q95. What is meant by scaling in VLSI design? Describe various effects of scaling.
Q96. What is meant by 90nm technology?
Q97. What is a transmission gate, and what is its typical use in VLSI?
Q98. What is ASIP?
Q99. What are the differences between gate array ASIC and cell based ASIC?
Q100. When you want the production in bulk amount which design style you prefer? Justify?
Q101. State the importance of Lithography in VLSI design?
Q102. Power Optimization Techniques for deep sub micron?
Q103. Define congestion in routing?
Q104. What do you mean by rip-up and re-routing?
Q105. What is Yield in fabrication process?
我英语差 看不明白 先收藏了 慢慢研究 顶一下
这些问题很实用啊 谢谢小编分享
很好啊！
额 英语的