ARM处理器架构-----协处理器

rn id;

}

void ARM_CP15_SetPageTableBase(P_U32 TableAddress)

{

__asm { MCR P15, 0, TableAddress, c2, c0, 0; }

}

void ARM_CP15_SetDomainAccessControl(U32 flags)

{

__asm { MCR P15, 0, flags, c3, c0, 0; }

}

void ARM_CP15_ICacheFlush()

{

unsigned long dummy;

__asm { MCR p15, 0, dummy, c7, c5, 0; }

}

void ARM_CP15_DCacheFlush()

{

unsigned long dummy;

__asm { MCR p15, 0, dummy, c7, c6, 0; }

}

void ARM_CP15_CacheFlush()

{

unsigned long dummy;

__asm { MCR p15, 0, dummy, c7, c7, 0; }

}

void ARM_CP15_TLBFlush(void)

{

unsigned long dummy;

__asm { MCR P15, 0, dummy, c8, c7, 0; }

}

void ARM_CP15_ControlRegisterWrite(U32 flags)

{

__asm { MCR P15, 0, flags, c1, c0; }

}

void ARM_CP15_ControlRegisterOR(U32 flag)

{

__asm {

mrc p15,0,r0,c1,c0,0

mov r2,flag

orr r0,r2,r0

mcr p15,0,r0,c1,c0,0

}

}

void ARM_CP15_ControlRegisterAND(U32 flag)

{

__asm {

mrc p15,0,r0,c1,c0,0

mov r2,flag

and r0,r2,r0

mcr p15,0,r0,c1,c0,0

}

}

void ARM_MMU_Init(P_U32 TableAddress)

{

ARM_CP15_TLBFlush();

ARM_CP15_CacheFlush();

ARM_CP15_SetDomainAccessControl(0xFFFFFFFF);

ARM_CP15_SetPageTableBase(TableAddress);

}

void Enable_MMU (void)

{

__asm {

mrc p15,0,r0,c1,c0,0

mov r2, #0x00000001

orr r0,r2,r0

mcr p15,0,r0,c1,c0,0

}

printf("MMU enabledn");

}

void Disable_MMU (void)

{

__asm {

mrc p15,0,r0,c1,c0,0

mov r2, #0xFFFFFFFE

and r0,r2,r0

mcr p15,0,r0,c1,c0,0

}

printf("MMU disabledn");

}