ARM的44binit.s文件的详细注释
CMP r0, r1 ; Check that they are different
BEQ ?
0
CMP r1, r3 ; Copy init data
LDRCC r2, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
STRCC r2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
BCC ?
1
LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
2
CMP r3, r1 ; Zero init
STRCC r2, [r3], #4
BCC ?
[ :LNOT:THUMBCODE
BL Main ;Dont use main() because ......;跳入main函数
B .
]
[ THUMBCODE ;for start-up code for Thumb mode
orr lr,pc,#1
bx lr
CODE16
bl Main ;Dont use main() because ......;跳入main函数
b .
CODE32
]
;4.初始化各模式下的栈指针
;****************************************************
;* The function for initializing stack *
;****************************************************
InitStacks
;Dont use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.50, msr cpsr,r1 can be used instead of msr cpsr_cxsf,r1
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack
;USER mode is not initialized.
mov pc,lr ;The LR register may be not valid for the mode changes.
;下面是pwdn模式下的相关寄存器的定义
;****************************************************
;* The function for entering power down mode *
;****************************************************
;void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;r0=CLKCON
ldr r0,=REFRESH
ldr r3,[r0]
mov r1, r3
orr r1, r1, #0x400000 ;self-refresh enable
str r1, [r0]
nop ;Wait until self-refresh is issued. May not be needed.
nop ;If the other bus master holds the bus, ...
nop ; mov r0, r0
nop
nop
nop
nop
;enter POWERDN mode
ldr r0,=CLKCON
str r2,[r0]
;wait until enter SL_IDLE,STOP mode and until wake-up
mov r0,#0xff
0 subs r0,r0,#1
bne ?
;exit from DRAM/SDRAM self refresh mode.
ldr r0,=REFRESH
str r3,[r0]
mov pc,lr
LTORG
;这是上面提到的对存储寄存器初始化的数据map
SMRDATA DATA
;*****************************************************************
;* Memory configuration has to be optimized for best performance *
;* The following parameter is not optimized. *
;*****************************************************************
;*** memory access cycle parameter strategy ***
; 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
; 2) The memory settings,here, are made the safe parameters even at 66Mhz.
; 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
; 4) DRAM refresh rate is for 40Mhz.
DCD 0x11110090 ;Bank0=OM[1:0], Bank1~Bank7=16bit, bank2=8bit;
DCD ((B0_Tacs<13)+(B0_Tcos<11)+(B0_Tacc<8)+(B0_Tcoh<6)+(B0_Tah<4)+(B0_Tacp<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<13)+(B1_Tcos<11)+(B1_Tacc<8)+(B1_Tcoh<6)+(B1_Tah<4)+(B1_Tacp<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<13)+(B2_Tcos<11)+(B2_Tacc<8)+(B2_Tcoh<6)+(B2_Tah<4)+(B2_Tacp<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<13)+(B3_Tcos<11)+(B3_Tacc<8)+(B3_Tcoh<6)+(B3_Tah<4)+(B3_Tacp<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<13)+(B4_Tcos<11)+(B4_Tacc<8)+(B4_Tcoh<6)+(B4_Tah<4)+(B4_Tacp<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<13)+(B5_Tcos<11)+(B5_Tacc<8)+(B5_Tcoh<6)+(B5_Tah<4)+(B5_Tacp<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<15)+(B6_Trcd<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<15)+(B7_Trcd<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<23)+(TREFMD<22)+(Trp<20)+(Trc<18)+(Tchr<16)+REFCNT) ;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
DCD 0x16 ;SCLK power mode, BANKSIZE 32M/32M
DCD 0x20 ;MRSR6 CL=2clk
DCD 0x20 ;MRSR7
ALIGN
;下面是对ram区域map的定义
AREA RamData, DATA, READWRITE
;这里定义了处理器工作于各模式的堆栈区在ram中map
^ (_ISR_STARTADDRESS-0x500)
UserStack # 256 ;c1(c7)ffa00
SVCStack # 256 ;c1(c7)ffb00
UndefStack # 256 ;c1(c7)ffc00
AbortStack # 256 ;c1(c7)ffd00
IRQStack # 256 ;c1(c7)ffe00
FIQStack # 0 ;c1(c7)fff00
;这里将中断异常向量建立在sdram中
^ _ISR_STARTADDRESS
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;Dont use the label IntVectorTable,
;because armasm.exe cannt recognize this label correctly.
;the value is different with an address you think it may be.
;IntVectorTable
HandleADC # 4
HandleRTC # 4
HandleUTXD1 # 4
HandleUTXD0 # 4
HandleSIO # 4
HandleIIC # 4
HandleURXD1 # 4
HandleURXD0 # 4
HandleTIMER5 # 4
HandleTIMER4 # 4
HandleTIMER3 # 4
HandleTIMER2 # 4
HandleTIMER1 # 4
HandleTIMER0 # 4
HandleUERR01 # 4
HandleWDT # 4
HandleBDMA1 # 4
HandleBDMA0 # 4
HandleZDMA1 # 4
HandleZDMA0 # 4
HandleTICK # 4
HandleEINT4567 # 4
HandleEINT3 # 4
HandleEINT2 # 4
HandleEINT1 # 4
HandleEINT0 # 4 ;0xc1(c7)fff84
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