msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack ; FIQStack=0x33FF_8000
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack ; SVCStack=0x33FF_5800
;USER mode has not be initialized.
;//为什么不用初始化user的stacks，系统刚启动的时候运行在哪个模式下？？？？？？？？？？？？？？？？？？？
mov pc,lr
;The LR register wont be valid if the current mode is not SVC mode.？？？？？？？？？？？？？
;//系统一开始运行就是SVCmode？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？
;=====================================================================
; Clock division test
; Assemble code, because VSYNC time is very short
;=====================================================================
EXPORT CLKdiv124
EXPORT CLKdiv144
CLKdiv124
ldr r0, = CLKdivN
ldr r1, = 0x3 ; 0x3 = 1:2:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<8)
orr r1, r1, #0x470 ; REFCNT135
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
CLKdiv144
ldr r0, = CLKdivN
ldr r1, = 0x4 ; 0x4 = 1:4:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<8)
orr r1, r1, #0x630 ; REFCNT675 - 1520
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
;存储器控制寄存器的定义区
LTORG
SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.
DCD (0+(B1_BWSCON<4)+(B2_BWSCON<8)+(B3_BWSCON<12)+(B4_BWSCON<16)+(B5_BWSCON<20)+(B6_BWSCON<24)+(B7_BWSCON<28))
DCD ((B0_Tacs<13)+(B0_Tcos<11)+(B0_Tacc<8)+(B0_Tcoh<6)+(B0_Tah<4)+(B0_Tacp<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<13)+(B1_Tcos<11)+(B1_Tacc<8)+(B1_Tcoh<6)+(B1_Tah<4)+(B1_Tacp<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<13)+(B2_Tcos<11)+(B2_Tacc<8)+(B2_Tcoh<6)+(B2_Tah<4)+(B2_Tacp<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<13)+(B3_Tcos<11)+(B3_Tacc<8)+(B3_Tcoh<6)+(B3_Tah<4)+(B3_Tacp<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<13)+(B4_Tcos<11)+(B4_Tacc<8)+(B4_Tcoh<6)+(B4_Tah<4)+(B4_Tacp<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<13)+(B5_Tcos<11)+(B5_Tacc<8)+(B5_Tcoh<6)+(B5_Tah<4)+(B5_Tacp<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<15)+(B6_Trcd<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<15)+(B7_Trcd<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<23)+(TREFMD<22)+(Trp<20)+(Trc<18)+(Tchr<16)+REFCNT)
DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7 CL=3clk
ALIGN
AREA RamData, DATA, READWRITE
^ _ISR_STARTADDRESS ; _ISR_STARTADDRESS=0x33FF_FF00
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;Dont use the label IntVectorTable,
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
;@0x33FF_FF20
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4_7 # 4
HandleEINT8_23 # 4
HandleCAM # 4 ; Added for 2440.
HandleBATFLT # 4
HandleTICK # 4
HandleWDT # 4
HandleTIMER0 # 4
HandleTIMER1 # 4
HandleTIMER2 # 4
HandleTIMER3 # 4
HandleTIMER4 # 4
HandleUART2 # 4
;@0x33FF_FF60
HandleLCD # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleDMA2 # 4
HandleDMA3 # 4
HandleMMC # 4
HandleSPI0 # 4
HandleUART1 # 4
HandleNFCON # 4 ; Added for 2440.
HandleUSBD # 4
HandleUSBH # 4
HandleIIC # 4
HandleUART0 # 4
HandleSPI1 # 4
HandleRTC # 4
HandleADC # 4
;@0x33FF_FFA0
END
