ARM协处理器CP15设置MMU，cache等学习

MRC p15,0,Rd,c0,c0,0 ; returns ID register

——芯片ID代表含义

Table 2-5 Register 0, ID code
Register bits FunctionValue
31:24 ——Implementer0x41——这个是什么意思？
23:20—— Specification revision0x1
19:16 ——Architecture (ARMv4T)0x2
15:4—— Part number0x920
3:0 ——Layout revision Revision

————————————————————————————————————————

2.3.4 Register 0, cache type register

This is a read-only register that contains information about the size and architecture of
the caches, allowing operating systems to establish how to perform such operations as
cache cleaning and lockdown. All ARMv4T and later cached processors contain this
register, allowing RTOS vendors to produce future-proof versions of their operating
systems.

You can access the cache type register by reading CP15 register 0 with theopcode_2 field
set to 1. For example:
MRC p15,0,Rd,c0,c0,1 ; returns cache details