U-boot1.1.6移植到TQ2440开发板(上)

volatileunsignedchar*p = (volatileunsignedchar*)&s3c2440nand->

s3c2440nand->

s3c2440nand->

volatileunsignedchar*p = (volatileunsignedchar*)&s3c2440nand->

volatileunsignedchar*p = (volatileunsignedchar*)&s3c2440nand->

*p = (addr >>

*p = (addr >>

*p = (addr >>

volatileunsignedchar*p = (volatileunsignedchar*)&s3c2440nand->

*p = (col >>

*p = (page >>

*p = (page >>

volatileunsignedchar*p = (volatileunsignedchar*)&s3c2440nand->

dr_lp(addr);

}

staticunsignedcharread_data(void)

{

returns3c2440_read_data();

}

voidnand_init_ll(void)

{

S3C2440_NAND* s3c2440nand = (S3C2440_NAND*)0x4e000000;

#defineTACLS 0

#defineTWRPH0 3

#defineTWRPH1 0

//设置时序

s3c2440nand->NFCONF= (TACLS<12)|(TWRPH0<8)|(TWRPH1<4);

// 使能NAND Flash控制器, 初始化ECC, 禁止片选

s3c2440nand->NFCONT= (1<4)|(1<1)|(1<0);

// 复位NAND Flash

nand_reset();

}

#if1

intNF_ReadID(void)

{

charpMID;

charpDID;

int nBuff;

char n4thcycle;

inti;

S3C2440_NAND* s3c2440nand = (S3C2440_NAND*)0x4e000000;

volatileunsignedchar*p = (volatileunsignedchar*)&s3c2440nand->NFADDR;

b128MB = 1;

n4thcycle = nBuff = 0;

nand_init_ll();

nand_select_chip();

write_cmd(0x90); // read id command

*p=0x00 & 0xff;

for( i = 0; i < 100; i++ );

pMID = read_data();

pDID = read_data();

nBuff = read_data();

n4thcycle = read_data();

nand_deselect_chip();

if(pDID >= 0xA0)

{

b128MB = 0;

}

return(pDID);

}

#endif

intnand_read_ll(unsignedchar*buf, unsignedlongstart_addr, intsize)

{

inti, j;

chardat;

S3C2440_NAND* s3c2440nand = (S3C2440_NAND*)0x4e000000;

volatileunsignedchar*p = (volatileunsignedchar*)&s3c2440nand->NFADDR;

if((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK))

{

return-1;

}

nand_select_chip();

for(i=start_addr; i < (start_addr + size);)

{

if(1){

write_cmd(0x50);

*p = 5;

for(j=0; j<10; j++);

*p = (i >> 9) & 0xff;

for(j=0; j<10; j++);

*p = (i >> 17) & 0xff;

for(j=0; j<10; j++);

*p = (i >> 25) & 0xff;

for(j=0; j<10; j++);

wait_idle();

dat = read_data();

write_cmd(0);

nand_deselect_chip();

if(dat != 0xff)

{

i += 16384; // 1 Block = 512*32= 16384

printf("Bad block at 0x%lx,will be skipped1n",i);

}

nand_select_chip();

}

write_cmd(0);

write_addr(i);

wait_idle();

for(j=0; j < NAND_SECTOR_SIZE; j++, i++)

{

*buf = read_data();

buf++;

}

}

nand_deselect_chip();

return0;

}

intnand_read_ll_lp(unsignedchar*buf, unsignedlongstart_addr, intsize)

{

inti, j;

chardat;

S3C2440_NAND* s3c2440nand = (S3C2440_NAND*)0x4e000000;

volatileunsignedchar*p = (volatileunsignedchar*)&s3c2440nand->NFADDR;

if((start_addr & NAND_BLOCK_MASK_LP) || (size & NAND_BLOCK_MASK_LP))

{

return-1;

}

nand_select_chip();

for(i=start_addr; i < (start_addr + size);)

{

if(1){

intcol, page;

col = i & NAND_BLOCK_MASK_LP;

page = i / NAND_SECTOR_SIZE_LP;

write_cmd(0x00);

*p = 5;

for(j=0; j<10; j++);

*p = 8;

for(j=0; j<10; j++);

*p = page & 0xff;

for(j=0; j<10; j++);

*p = (page >> 8) & 0xff;

for(j=0; j<10; j++);

if(b128MB == 0)

*p = (page >> 16) & 0x03;

for(j=0; j<10; j++);

write_cmd(0x30);

wait_idle();

dat = read_data();

nand_deselect_chip();

if(dat != 0xff)

{

i += 131072; // 1 Block = 2048*64= 131072

}

nand_select_chip();

}

write_cmd(0);

write_addr_lp(i);

write_cmd(0x30);

wait_idle();

for(j=0; j < NAND_SECTOR_SIZE_LP; j++, i++)

{

*buf = read_data();

buf++;

}

}

nand_deselect_chip();

return0;

}

intbBootFrmNORFlash(void)

{

volatileunsignedint*pdw = (volatileunsignedint*)0;

unsignedintdwVal;

dwVal = *pdw;

*pdw = 0x12345678;

if(*pdw != 0x12345678)

{

return1;

}

else

{

*pdw = dwVal;

return0;

}

}

intCopyCode2Ram(unsignedlongstart_addr, unsignedchar*buf, intsize)

{

unsignedint*pdwDest;

unsignedint*pdwSrc;

inti;

long*GPBCON=0x56000010;

long*GPBDAT=0x56000014;

long*GPBUP =0x56000018;

*GPBCON=0x295551;

*GPBUP=0xff;

*GPBDAT=0x7be;

if(bBootFrmNORFlash())

{

pdwDest = (unsignedint*)buf;

pdwSrc = (unsignedint*)start_addr;

for(i = 0; i < size / 4; i++)

{

pdwDest[i] = pdwSrc[i];

}

return0;

}

else

{

nand_init_ll();

if(NF_ReadID() == 0x76 )

{

nand_read_ll(buf, start_addr, (size + NAND_BLOCK_MASK)&~(NAND_BLOCK_MASK));}

else

{

nand_read_ll_lp(buf, start_addr, (size + NAND_BLOCK_MASK_LP)&~(NAND_BLOCK_MASK_LP));}

return0;

}

}

staticinlinevoiddelay(unsignedlongloops)

{

__asm__volatile("1:n"

"subs %0, %1, #1n"

"bne1b":"=r"(loops):"0"(loops));

}

#defineS3C2440_MPLL_400MHZ ((0x5c<12)|(0x01<4)|(0x01)) //HJ 400MHz

#defineS3C2440_MPLL_405MHZ ((0x7f<12)|(0x02<4)|(0x01)) //HJ 405MHz

#defineS3C2440_MPLL_440MHZ ((0x66<12)|(0x01<4)|(0x01)) //HJ 440MHz

#defineS3C2440_MPLL_480MHZ ((0x98<12)|(0x02<4)|(0x01)) //HJ 480MHz

#defineS3C2440_MPLL_200MHZ ((0x5c<12)|(0x01<4)|(0x02))

#defineS3C2440_MPLL_10