PIC 、APIC(IOAPIC LAPIC)

[13] Interrupt Input Pin Polarity (INTPOL)—R/W.This bit specifies the polarity of the interrupt

signal. 0=High active, 1=Low active.

[12]Delivery Status (DELIVS)—RO.The Delivery Status bit contains the current status of the

delivery of this interrupt. Delivery Status is read-only and writes to this bit (as part of a 32 bit

word) do not effect this bit. 0=IDLE (there is currently no activity for this interrupt). 1=Send

Pending (the interrupt has been injected but its delivery is temporarily held up due to the APIC

bus being busy or the inability of the receiving APIC unit to accept that interrupt at that time).

[11] Destination Mode (DESTMOD)—R/W.This field determines the interpretation of the

Destination field. When DESTMOD=0 (physical mode), a destination APIC is identified by its ID.

Bits 56 through 59 of the Destination field specify the 4 bit APIC ID. When DESTMOD=1 (logical mode), destinations are identified by matching on the logical destination under the control of theDestination Format Register and Logical Destination Register in each Local APIC.

Destination Mode IOREDTBLx[11] Logical Destination Address 0, Physical Mode IOREDTBLx[59:56] = APIC ID1, Logical Mode IOREDTBLx[63:56] = Set of processorsE 82093AA (IOAPIC)

[10:8]Delivery Mode (DELMOD)—R/W.The Delivery Mode is a 3 bit field that specifies how the APICs listed in the destination field should act upon reception of this signal. Note that certain

Delivery Modes only operate as intended when used in conjunction with a specific trigger Mode.

These restrictions are indicated in the following table for each Delivery Mode.

Mode Description

000Fixed Deliver the signal on the INTR signal of all processor cores listed in the

destination. Trigger Mode for "fixed" Delivery Mode can be edge or level.

001Lowest

Priority Deliver the signal on the INTR signal of the processor core that is

executing at the lowest priority among all the processors listed in the

specified destination. Trigger Mode for "lowest priority". Delivery Mode

can be edge or level.

010SMI System Management Interrupt. A delivery mode equal to SMI requires an

edge trigger mode. The vector information is ignored but must be

programmed to all zeroes for future compatibility.

011Reserved

100NMI Deliver the signal on the NMI signal of all processor cores listed in the

destination. Vector information is ignored. NMI is treated as an edge

triggered interrupt, even if it is programmed as a level triggered interrupt.

For proper operation, this redirection table entry must be programmed to

“edge” triggered interrupt.

101INIT Deliver the signal to all processor cores listed in the destination by

asserting the INIT signal. All addressed local APICs will assume their

INIT state. INIT is always treated as an edge triggered interrupt, even if

programmed otherwise. For proper operation, this redirection table entry

must be programmed to “edge” triggered interrupt.

110Reserved

111ExtINT Deliver the signal to the INTR signal of all processor cores listed in the

destination as an interrupt that originated in an externally connected

(8259A-compatible) interrupt controller. The INTA cycle that corresponds

to this ExtINT delivery is routed to the external controller that is expected

to