数字输入输出端口的平均和最大电流计算
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结论
不仅对于板级应用,在芯片的设计阶段I/O管脚和模组的电源完整性性能也是一项重点考量项目。在芯片设计的前期阶段I/O设计团队也需要在具体设计完成之前提前提供电流消耗的估算结果,这样才能使整个芯片各个模块的设计配合无误。对于更复杂更精确的电流消耗分析需要借助电源完整性仿真工具的帮助。本文中级介绍的两个公式可以实现快速估算I/O的平均和最大电流。飞思卡尔的I/O设计和应用团队通过对i.MX系列应用处理器的设计验证,证实了公式可以提供相对精确的估算结果。
References
[1]. Henry W. Ott, (2009). “Electromagnetic Compatibility
Engineering”, ISBN 978-0-470-18930-6pp. 428.
[2]. Lee W. Ritchey, “Right The First Time - A Practical Handbook On High-Speed PCB and System Design”, pp. 353.
[3]. Freescale Semiconductor i.MX6 series applications processors Datasheet at http://www.freescale.com/
webapp/sps/site/prod_summary.jsp?code=i.MX6Q&fpsp=1&tab=Documentation_Tab
[4]. Vishram S. Pandit, Woong Hwan Ryu, Myoung Joon Choi, “Power Integrity for I/O Interfaces: With Signal
Integrity/ Power Integrity Co-Design (Prentice Hall Signal Integrity Library)”, ISSBN -13: 970-0-137-01119-3, pp. 1-383.
[5] M. Swaminathan, E. Engin, “Power Integrity Modeling and Design for Semiconductors and Systems”, Prentice
Hall, press.
[6]. M.J. Choi, and V. Pandit, (2009). “SI/PI Co-Analysis for I/O Interfaces,” IBIS Summit.
[7]. Eric Bogatin, (2009). “Signal and Power Integrity – Simplified2nd Edition”, Hardback.
[8]. Masanori Hashimoto & Raj Nair, (2011). “Power Integrity for Nanoscale Integrated Systems”, A practical handbook for designing with power supply noise.
[9]. Vishram S. Pandit and others, (2009). “SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity”, DESIGNCON.
[10]. I. Novak (2008). (Executive Editor), “Power Distribution Design Methodologies” IEC, ISBN: 978-1-931695-65-7.
不仅对于板级应用,在芯片的设计阶段I/O管脚和模组的电源完整性性能也是一项重点考量项目。在芯片设计的前期阶段I/O设计团队也需要在具体设计完成之前提前提供电流消耗的估算结果,这样才能使整个芯片各个模块的设计配合无误。对于更复杂更精确的电流消耗分析需要借助电源完整性仿真工具的帮助。本文中级介绍的两个公式可以实现快速估算I/O的平均和最大电流。飞思卡尔的I/O设计和应用团队通过对i.MX系列应用处理器的设计验证,证实了公式可以提供相对精确的估算结果。
References
[1]. Henry W. Ott, (2009). “Electromagnetic Compatibility
Engineering”, ISBN 978-0-470-18930-6pp. 428.
[2]. Lee W. Ritchey, “Right The First Time - A Practical Handbook On High-Speed PCB and System Design”, pp. 353.
[3]. Freescale Semiconductor i.MX6 series applications processors Datasheet at http://www.freescale.com/
webapp/sps/site/prod_summary.jsp?code=i.MX6Q&fpsp=1&tab=Documentation_Tab
[4]. Vishram S. Pandit, Woong Hwan Ryu, Myoung Joon Choi, “Power Integrity for I/O Interfaces: With Signal
Integrity/ Power Integrity Co-Design (Prentice Hall Signal Integrity Library)”, ISSBN -13: 970-0-137-01119-3, pp. 1-383.
[5] M. Swaminathan, E. Engin, “Power Integrity Modeling and Design for Semiconductors and Systems”, Prentice
Hall, press.
[6]. M.J. Choi, and V. Pandit, (2009). “SI/PI Co-Analysis for I/O Interfaces,” IBIS Summit.
[7]. Eric Bogatin, (2009). “Signal and Power Integrity – Simplified2nd Edition”, Hardback.
[8]. Masanori Hashimoto & Raj Nair, (2011). “Power Integrity for Nanoscale Integrated Systems”, A practical handbook for designing with power supply noise.
[9]. Vishram S. Pandit and others, (2009). “SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity”, DESIGNCON.
[10]. I. Novak (2008). (Executive Editor), “Power Distribution Design Methodologies” IEC, ISBN: 978-1-931695-65-7.
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