视频解码器ADV7181B：硬件和软件设计要点

模拟器件公司(ADI)的ADV7181B解码器|0">

; Convert from SD RGB to SD YPrPb

42 62 20; Convert from SD RGB to SD YPrPb

42 63 03; Convert from SD RGB to SD YPrPb

42 64 A9; Convert from SD RGB to SD YPrPb

42 65 1A; Convert from SD RGB to SD YPrPb

42 66 B8; Convert from SD RGB to SD YPrPb

42 67 03; Convert from SD RGB to SD YPrPb

42 68 00; Convert from SD RGB to SD YPrPb

42 6A 80; Enable 27 MHz LLC output

42 6B C3; Select the 8-bit YPrPb from the special mode output formatter

42 73 D0; Manual gain control

42 74 B4; GAIN setting

42 7B 06; Special mode write to ensure 656 compliant SAV/EAV codes

42 C3 C9; Mux AIN1 to ADC0; mux AIN3 to ADC1

42 C4 8D; Set adc_sw_man_en to 1, mux AIN5 to ADC2

42 85 1A; Enable the sync input mode on Pin 50

42 86 02; Enable the internal special mode sync slicer block

42 B3 FE; SCART RGB write

42 C9 0C; Enable DDR Mode, enable DDR_I2C_RC_First (writing this sequence ensures a 27 MHz output clock)

42 0E 80; Enable design block tweak mode

42 58 ED; Internal timing optimization, not user adjustable

42 90 C9; Internal timing optimization, not user adjustable

42 91 40; internal timing optimization, not user adjustable

42 92 3C; Internal timing optimization, not user adjustable

42 93 CA; Internal timing optimization, not user adjustable

42 94 D5; Internal timing optimization, not user adjustable

42 CF 7C; Internal timing optimization, not user adjustable

42 D0 4E; Internal timing optimization, not user adjustable

42 D6 DD; Internal timing optimization, not user adjustable

42 E5 51; Internal timing optimization, not user adjustable

42 0E 00; Close design block