QorIQ Qonverge B4860 SoC基带处理器深层剖析

simultaneous multi threading (SMT) 128-bit AltiVec SIMD unit 40-bit physical addressing Fully featured MMU with a 1024-entry eight-way set-associative cache Core virtualization supporting hypervisor and logical to real address translation Clustered L2 cache allowing strict allocation or full sharing Hardware support for L1 and L2 cache coherency DPAA (frame manager, queue manager, buffer manager) for IP packed acceleration Security protocol accelerators: SNOW-3G, Kasumi, ZUC, IPSec, DES, 3DES, AES, MD5, SHA-1/2, HMAC Integrated DSP cores and baseband accelerators for layer 1 processing Six StarCore SC3900FP FVP programmable cores - Up to 32 MAC/cycle of 16-bit and up to 16 FLOP/cycle - Eight instructions per cycle - Up to eight data lanes vector in a single instruction (SIMD8) - State-of-the-art support for control code with branch prediction - Fully featured memory management unit and logical to real address translation - Clustered L2 cache allowing strict allocation or full sharing - Hardware support for L1 and L2 cache coherency MAPLE baseband accelerators FEC accelerators for LTE, LTE-Advanced and WCDMA

Turbo decoder with rate de-matching and HARQ combining

Turbo encoder with rate matching Viterbi decoder

FFT/iFFT

DFT/iDFT

MiMO equalizer MMSE-based supporting IRC, SIC and PIC Matrix inversion and multipliation PUSCH data path embedded flow PDSCH data path embedded flow WCDMA/HSPA+ chip rate and path search CRC

CoreNet: Internal cache coherent switch fabric enabling full cache coherent system

wo DDR-3/3L controllers: 64-bit, 1.867 GHz (each with 512 KB L3 cache)

ECC support for on-chip and off-chip memories

High-speed interfaces multiplexed into 16 SerDes 10G ports

Two 10G/2.5G/1G Ethernet controllersFour 2.5G/1G Ethernet controllers

IEEE 1588v2 support

Two x4 Serial RapidIO controllers 5G (Gen II)

Eight CPRI v4.2 controllers 9.8G

Four-lane PCI Express 5G (Gen II)

Eight Aurora: Tracing/debug

Trust architecture with secure boot One serial port interface (eSPI) One eSD/eMMC interface One IFC: 16-bit integrated NAND/NOR flash controller or general-purpose interface One USB 2.0 interface Four I2C Interfaces Four UART ports 182 32-bit timers 44 general-purpose I/Os

软件

Development tools from Freescale and partners Eclipse IDE Compilers Debuggers Profiling, critical code analysis, call tree, trace points Nexus trace viewer, code viewer, performance view, trace analyzer Scripting for post-process trace and performance data Register analyzer Device and core simulators Operating systems BSP and device drivers B4860QDS board: Software and reference application development system Freescale’s optimized software reference libraries for LTE and WCDMA layer 1 PHY functions General 1020-pin FC-PBGA package, 1 mm pitch Core voltage: VID I/O voltage: 1, 1.2, 1.35, 1.5, 1.8 and 2.5 nominal Industrial temperature range 12.3 MB internal memory Debug ports: Test access port and boundary scan architecture compliant with IEEE Std. 1149.1,1149.6 and Nexus IEEE-ISTO 5001 trace support Lead-free ROHS compliant

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QorIQ Qonverge B4860基带处理器概述

摘 要：QorIQ Qonverge B4860片上系统适用于新一代多标准无线基站。B4860基于28纳米工艺技术，吞吐量和容量达到无以伦比的水平，不仅具有高效、高性能可编程内核，还 配有应用专用加速器，实现最佳的性价比。它专门针对宽带无线通信基础设施的宏蜂窝基站设计，采用我