PowerPC简介及编程
1.32位PowerPC结构特点
32个32位通用寄存器 ( GPRs )
寄存器支持用户级指令集 (不包括浮点指令),包括integer exception register (XER ),condition register(CR),link register(LR),counter register ( CTR )
时间加减及寄存器
管理级寄存器,与PowerPC定义兼容
Configuration-----Machine Status Register ( MSR )
Exception model-----Save/restore registers 0 and 1 (SRR0 and SRR1), DSI status register ( DSISR ), data address register ( DAR )
PowerPC 减量器
PowerPC 时基和 实时时钟(RTC)
2.地址映射
名称 | 内存物理地址 | 备注 |
SDRAM | 0x00000000~0x7FFFFFFF | |
PCI | 0x80000000~0xEF5FFFFF | |
Internal Peripherals | 0xEF600000~0xEFFFFFFF | |
UART | ..... | |
..... | ..... | |
External Peripherals | 0xF0000000~0xFF7FFFFF | |
NVRAM/RTC | 0xF0000000~0xF0001FFF | (8K)下画线为片选 |
Keybord/Mouse | 0xF0100000~0xF0100001 | 下画线为片选 |
FPGA_INT_ST.. | 0xF0300000~0xF0300000 | 下画线为片选 |
FPGA_INT_EN.. | 0xF0300001~0xF0300001 | 下画线为片选 |
Socket Flash | 0xFFF80000~0xFFFFFFFF | 512K |
SRAM | 0xFFF00000~0xFFF7FFFF | 512K(可通过Swich与Socket Flash 切换) |
3.中断优先级(Exception Priority)
Priority | Exception Type | Cause |
1 | Development port | nonmaskable interrupt Signal from the development port |
2 | System reset | interrupt IRQ0 assertion |
3 | Instruction-related exceptions | Instruction processing |
4 | Peripheral breakpoint request or development port maskable interrupt | Breakpoint signal from any peripheral |
5 | External interrupt (masked if MSR[EE] = 0) | Signal from the interrupt controller |
6 | Decrementer interrupt(masked if MSR[EE] = 0) | Decrementer request |
4.中断向量表
中断向量表的起始地址取决于MSR[IP]的设置
MSR[IP]=0 Exceptions are vectored to the physical address 0x000n_nnnn
MSR[IP]=1 Exceptions are vectored to the physical address 0xFFFn_nnnn
Offset | Exception | Description |
0x00000 | Reserved | |
0x00100 | System reset interrupt | |
0x00200 | Machine check interrupt | |
0x00300 | DSI | A DSI exception is never generated by hardware, but software may branch to this location because of an data TLB error or miss exception. |
0x00400 | ISI | An ISI exception is never generated by the hardware, but software may branch to this location because of an implementation-speciTc instruction TLB error exception. |
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