新手求助,DDS里的查找表模块出了点问题
时间:10-02
整理:3721RD
点击:
拜托帮忙看下,感激不尽。
需要做一个DDS,其中的查找表模块在波形仿真时出现问题,如图:
![](../imgqa/pcb/pcb-124540va3aa6hcaf335zh27395.png)
仿真后:
![](../imgqa/pcb/pcb-124626u6pe3fbprryvrlqf7396.png)
这是我的代码:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ROM IS
PORT (ADDR:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
CLK:IN STD_LOGIC;
OUTP:OUT SIGNED (7 DOWNTO 0));
END ENTITY ROM;
ARCHITECTURE ART OF ROM IS
BEGIN
PROCESS (CLK) IS
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
CASE ADDR IS
WHEN "00000000"=>OUTP<="00000000";
WHEN "00000001"=>OUTP<="00000010";
WHEN "00000010"=>OUTP<="00000011";
WHEN "00000011"=>OUTP<="00000101";
WHEN "00000100"=>OUTP<="00000110";
WHEN "00000101"=>OUTP<="00001000";
WHEN "00000110"=>OUTP<="00001001";
WHEN "00000111"=>OUTP<="00001011";
WHEN "00001000"=>OUTP<="00001101";
WHEN "00001001"=>OUTP<="00001110";
WHEN "00001010"=>OUTP<="00010000";
WHEN "11101001"=>OUTP<="11011100";
WHEN "11101010"=>OUTP<="11011110";
WHEN "11101011"=>OUTP<="11011111";
WHEN "11101100"=>OUTP<="11100001";
WHEN "11101101"=>OUTP<="11100010";
WHEN "11101110"=>OUTP<="11100100";
WHEN "11101111"=>OUTP<="11100101";
WHEN "11110000"=>OUTP<="11100111";
WHEN "11110001"=>OUTP<="11101001";
WHEN "11110010"=>OUTP<="11101010";
WHEN "11110011"=>OUTP<="11101100";
WHEN "11110100"=>OUTP<="11101101";
WHEN "11110101"=>OUTP<="11101111";
WHEN "11110110"=>OUTP<="11110000";
WHEN "11110111"=>OUTP<="11110010";
WHEN "11111000"=>OUTP<="11110011";
WHEN "11111001"=>OUTP<="11110101";
WHEN "11111010"=>OUTP<="11110111";
WHEN "11111011"=>OUTP<="11111010";
WHEN "11111100"=>OUTP<="11111011";
WHEN "11111101"=>OUTP<="11111101";
WHEN "11111110"=>OUTP<="11111110";
WHEN "11111111"=>OUTP<="00000000";
WHEN OTHERS=>OUTP<="00000000";
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE ART;
拜托大家帮我看一下,感激不尽。
需要做一个DDS,其中的查找表模块在波形仿真时出现问题,如图:
![](../imgqa/pcb/pcb-124540va3aa6hcaf335zh27395.png)
仿真后:
![](../imgqa/pcb/pcb-124626u6pe3fbprryvrlqf7396.png)
这是我的代码:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ROM IS
PORT (ADDR:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
CLK:IN STD_LOGIC;
OUTP:OUT SIGNED (7 DOWNTO 0));
END ENTITY ROM;
ARCHITECTURE ART OF ROM IS
BEGIN
PROCESS (CLK) IS
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
CASE ADDR IS
WHEN "00000000"=>OUTP<="00000000";
WHEN "00000001"=>OUTP<="00000010";
WHEN "00000010"=>OUTP<="00000011";
WHEN "00000011"=>OUTP<="00000101";
WHEN "00000100"=>OUTP<="00000110";
WHEN "00000101"=>OUTP<="00001000";
WHEN "00000110"=>OUTP<="00001001";
WHEN "00000111"=>OUTP<="00001011";
WHEN "00001000"=>OUTP<="00001101";
WHEN "00001001"=>OUTP<="00001110";
WHEN "00001010"=>OUTP<="00010000";
WHEN "11101001"=>OUTP<="11011100";
WHEN "11101010"=>OUTP<="11011110";
WHEN "11101011"=>OUTP<="11011111";
WHEN "11101100"=>OUTP<="11100001";
WHEN "11101101"=>OUTP<="11100010";
WHEN "11101110"=>OUTP<="11100100";
WHEN "11101111"=>OUTP<="11100101";
WHEN "11110000"=>OUTP<="11100111";
WHEN "11110001"=>OUTP<="11101001";
WHEN "11110010"=>OUTP<="11101010";
WHEN "11110011"=>OUTP<="11101100";
WHEN "11110100"=>OUTP<="11101101";
WHEN "11110101"=>OUTP<="11101111";
WHEN "11110110"=>OUTP<="11110000";
WHEN "11110111"=>OUTP<="11110010";
WHEN "11111000"=>OUTP<="11110011";
WHEN "11111001"=>OUTP<="11110101";
WHEN "11111010"=>OUTP<="11110111";
WHEN "11111011"=>OUTP<="11111010";
WHEN "11111100"=>OUTP<="11111011";
WHEN "11111101"=>OUTP<="11111101";
WHEN "11111110"=>OUTP<="11111110";
WHEN "11111111"=>OUTP<="00000000";
WHEN OTHERS=>OUTP<="00000000";
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE ART;
拜托大家帮我看一下,感激不尽。
求救啊啊啊求救啊啊啊啊!