用protel DXP做仿真,出现matrix is singular,什么原因?
![](../imgqa/pcb/pcb-155741etz9rhhlrtgggmlh8082.jpg)
这是电路图
错误提示:
[Error] RLC XSpice doAnalyses: Matrix is singular
为什么啊?怎么解决?
看一下下面的英文资料吧。
One of the challenges of all Simulators is convergence. What exactly is meant by the term, “convergence”? Like most Simulators, the Design Explorer-based Simulator's SPICE engine uses an iterative process of repeatedly solving the equations that represent your circuit, to find the quiescent circuit voltages and currents. If it fails to find these voltages and current (fails to converge) then it will not be able to perform an analysis of the circuit.
SPICE uses simultaneous linear equations, expressed in matrix form, to determine the operating point (DC voltages and currents) of a circuit at each step of the simulation. The circuit is reduced to an array of conductances which are placed in the matrix to form the equations (G * V = I). When a circuit includes nonlinear elements, SPICE uses multiple iterations of the linear equations to account for the non-linearities. SPICE makes an initial guess at the node voltages then calculates the branch currents based on the conductances in the circuit. SPICE then uses the branch currents to recalculate the node voltages, and the cycle is repeated. This cycle continues until all of the node voltages and branch currents fall within specified tolerances (converge).
However, if the voltages or currents do not converge within a specified number of iterations, SPICE produces error messages (such as “singular matrix”, “Gmin stepping failed”, “source stepping failed” or “iteration limit reached”) and aborts the simulation. SPICE uses the results of each simulation step as the initial guesses for the next step. If you are performing a Transient analysis (that is, time is being stepped) and SPICE cannot converge on a solution using the specified timestep, the timestep is automatically reduced, and the cycle is repeated. If the timestep is reduced too far, SPICE displays a “Timestep too small” message and aborts the simulation.
用词霸将singular matrix翻译为“退化(矩)阵, 降秩(矩)阵”,我也不是很理解。上面的一段我把它翻译成中文了。
对仿真的一大挑战便是“收敛”的实现。与大多数仿真器相同,Design Explorer-based Simulator's SPICE同样使用重复迭代的方式来获得当前电路的静态电压和电流值,如果无法获得这个值,仿真就无法实现,这种情况便称之为“收敛失败”。
SPICE使用以矩阵式表达的联立线性方程,决定了电路仿真每一步中电路测试点的直流电压值和电流值,整个电路可以表示为一系列电导系数,这些系数被放置到矩阵列中,并且满足G*V=1这个表达式。如果一个电路包含非线性元素,SPICE就采用多重线性迭代来解决非线性。SPICE首先对节点初始电压进行预测,然后根据电路的电导系数计算支路电流,接着用支路电流重新计算节点电压,一直这样进行着循环。这种循环一直持续到所有的节点电压和支路电流都落入规定的误差允许范围内(即收敛)。
如果节点电压和支路电流没有在一定数量的重复中完成收敛的话,SPICE将提示错误信息(例如“singular matrix”、“Gmin stepping failed”、 “source stepping failed”或者“iteration limit reached”),这样就无法实现仿真了。SPICE将前一步的仿真结果作为初始值用于下一步的仿真中,如果你正在进行电路的瞬态分析(也就是说,时间以timestep来确定),在你设置的某一timestep设置条件下无法实现收敛,这时timestep将自动被降低,继续重复上述的循环。如果timestep降低幅度太大,SPICE将提示“Timestep too small”,这时仿真失败。
怎么解决呢?
我也存在这样的问题,一直没能解决,看完这个软件的英文解决方案之后,个人觉得问题大概是出在参数设置方面,主要是需要更改design--simulation--mixed sim---advanced option里面的某些默认参数
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