用quartus II软件和大西瓜开发板做频率计的实验，如何减小输出频率的误差？

时间：10-02 整理：3721RD 点击：

详情请看EDA技术与VHDL第4版潘松编著（清华大学出版社）实验4-5
本人已经做好所有的原理图和程序，就是不知道如何降低输出的误差
比如我分频计用的是20分频，但是输出显示的是21
使用的分频器程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(clk: in std_logic;clk0_5Hz:out std_logic);
end fenpin;
architecture segled of fenpin is
begin
p1:process(clk)
variable count:integer range 0 to 6249999;
begin
if clk'event and clk='1' then
if count<=3124999 then
   clk0_5Hz<='0';
   count:=count+1;
   elsif count>3124999 and count<=6249999 then
            clk0_5Hz<='1';
            count:=count+1;
      else count:=0;
      end if;
      end if;
end process p1;
END ARCHITECTURE SEGLED;
测试用的分频器程序library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fenpin1 is
port(clk: in std_logic;clk1Hz:out std_logic);
end fenpin1;
architecture segled of fenpin1 is
begin
p1:process(clk)
variable count:integer range 0 to 49999999;
begin
if clk'event and clk='1' then
if count<=24999999 then
   clk1Hz<='0';
   count:=count+1;
   elsif count>24999999 and count<=49999999 then
            clk1Hz<='1';
            count:=count+1;
      else count:=0;
      end if;
      end if;
end process p1;
END ARCHITECTURE SEGLED;

2位十进制频率计顶层设计原理图文件.png